Re: [gem5-users] Error when building gem5

2018-06-21 Thread Tariq Azmy
Hi Jason,

No problem. I've never contributed patches to gerrit before, maybe I'll try
it next time :) Glad that it has been fixed. Thanks for the update.

On Wed, Jun 20, 2018 at 1:35 PM, Jason Lowe-Power 
wrote:

> Hi Tariq,
>
> Thanks for letting us know about this issue. Nikos just merged a change
> that fixes it: https://gem5-review.googlesource.com/c/public/gem5/+/11429
>
> Cheers,
> Jason
>
> On Tue, Jun 19, 2018 at 11:01 AM Jason Lowe-Power 
> wrote:
>
>> HI Tariq,
>>
>> You can fix it and submit a patch to gerrit :). Likely, you just need
>> #include  at the top of addr_range_map.hh.
>>
>> See https://gem5.googlesource.com/public/gem5/+/master/CONTRIBUTING.md
>> for more details.
>>
>> Cheers,
>> Jason
>>
>> On Tue, Jun 19, 2018 at 10:44 AM Tariq Azmy 
>> wrote:
>>
>>> Hi,
>>>
>>> I got a fresh new gem5 from google repo (https://gem5.googlesource.
>>> com/public/gem5) and built the X86 with scons. But there's an error
>>> from xbar:
>>>
>>> In file included from build/X86/mem/xbar.hh:57:0,
>>>  from build/X86/mem/noncoherent_xbar.hh:54,
>>>  from build/X86/mem/noncoherent_xbar.cc:50:
>>> build/X86/base/addr_range_map.hh:221:35: error: 'std::function' has not
>>> been declared
>>>  find(const AddrRange , std::function cond)
>>> const
>>>^~~~
>>> build/X86/base/addr_range_map.hh:221:43: error: expected ',' or '...'
>>> before '<' token
>>>  find(const AddrRange , std::function cond)
>>> const
>>>^
>>> scons: *** [build/X86/mem/noncoherent_xbar.o] Error 1
>>> scons: building terminated because of errors.
>>>
>>> Hope it can get fixed.
>>>
>>> Thanks
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Error when building gem5

2018-06-19 Thread Tariq Azmy
Hi,

I got a fresh new gem5 from google repo (
https://gem5.googlesource.com/public/gem5) and built the X86 with scons.
But there's an error from xbar:

In file included from build/X86/mem/xbar.hh:57:0,
 from build/X86/mem/noncoherent_xbar.hh:54,
 from build/X86/mem/noncoherent_xbar.cc:50:
build/X86/base/addr_range_map.hh:221:35: error: 'std::function' has not
been declared
 find(const AddrRange , std::function cond)
const
   ^~~~
build/X86/base/addr_range_map.hh:221:43: error: expected ',' or '...'
before '<' token
 find(const AddrRange , std::function cond)
const
   ^
scons: *** [build/X86/mem/noncoherent_xbar.o] Error 1
scons: building terminated because of errors.

Hope it can get fixed.

Thanks
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Reading the size of X86 register

2018-06-05 Thread Tariq Azmy
Hi,

Is there a way to access the data size of operand/destination register of
some instruction? For example, in mediaOpReg, there are uint8_t srcSize, as
well as uint8_t destSize but I believe these information don't get passed
to the super class, i.e. StaticInst, when it get constructed. Therefore I
couldn't access these info through staticInstPtr.

Thanks
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] x86 instructions with microops

2018-05-29 Thread Tariq Azmy
Hi,

How is a particular instruction being decoded, especially when it has
micro-ops? I looked at the stats in commit_impl.hh

if (!inst->isMicroop() || inst->isLastMicroop())
instsCommitted[tid]++;
opsCommitted[tid]++;

Does this means the micro ops is also stored as a Dynamic Inst, with
different PC address? Also where is the file(s) that shows list of
instruction that has microops?

Thanks
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] x86 floating point instruction

2018-05-28 Thread Tariq Azmy
Thanks Jason. I also came across the same document earlier but I just
wanted to ask about this in general.

On Mon, May 28, 2018 at 11:09 AM, Jason Lowe-Power 
wrote:

> Hi Tariq,
>
> It's up to you what you want the latency for SSE instructions to be. It
> depends on what architecture you're simulating. Unfortunately, we currently
> don't have any "known good" configurations for x86 cores so you'll have to
> come up with your own :). Here's some examples of numbers you could use.
> http://www.agner.org/optimize/instruction_tables.pdf
>
> Cheers,
> Jason
>
> On Fri, May 25, 2018 at 2:12 PM Tariq Azmy 
> wrote:
>
>> Hi Gabe, Jason,
>>
>> Are those x86 SIMD SSE arithmetic instructions take only one cycle as
>> latency? I looked into the FuncUnitConfig.py and seems like the op lats for
>> the SIMD functional units are not defined, so I assumed it takes value of 1
>> by default.
>>
>> I am not really familiar with x86 SIMD extension, so maybe this question
>> is more related to x86 ISA in general.
>>
>> Thanks.
>>
>> On Thu, May 24, 2018 at 9:52 AM, Jason Lowe-Power 
>> wrote:
>>
>>> Hi Tariq,
>>>
>>> It wold be great if you could review Gabe's patch on gerrit. Since it
>>> works for you, giving it a +1 or a +2 would be appropriate.
>>>
>>> Cheers,
>>> Jason
>>>
>>> On Wed, May 23, 2018 at 5:56 PM Tariq Azmy 
>>> wrote:
>>>
>>>> Thanks Gabe. Yeah it does not impact the program but it's just that the
>>>> statistic is incorrect.
>>>>
>>>> By the way, I applied the patch and stats now shows correct micro-ops
>>>> entries.
>>>>
>>>> Appreciate your help. Thanks again
>>>>
>>>> On Wed, May 23, 2018 at 6:51 PM, Gabe Black 
>>>> wrote:
>>>>
>>>>> Yep, those microops aren't given a operand class, and so the isa
>>>>> parser is guessing and making the FloatAddOp. I haven't really tested this
>>>>> beyond making sure it compiles, but here's a patch that might get this
>>>>> working for you.
>>>>>
>>>>> https://gem5-review.googlesource.com/c/public/gem5/+/10541
>>>>>
>>>>> Gabe
>>>>>
>>>>> On Wed, May 23, 2018 at 4:13 PM, Gabe Black 
>>>>> wrote:
>>>>>
>>>>>> I'm confident they aren't implemented with floating point add. It's
>>>>>> likely either that the microops are misclassified, or they're 
>>>>>> unimplemented
>>>>>> and printing a warning, but the fact that they don't actually do any math
>>>>>> isn't impacting your program for whatever reason. I'll take a quick look.
>>>>>>
>>>>>> Gabe
>>>>>>
>>>>>> On Wed, May 23, 2018 at 2:07 PM, Tariq Azmy 
>>>>>> wrote:
>>>>>>
>>>>>>> Hi,
>>>>>>>
>>>>>>> I wrote simple code that does simple floating point multiplication
>>>>>>> and division operation and from the assembly, I can see there are MULSS 
>>>>>>> and
>>>>>>> DIVSS instructions. But after I ran the simulation on gem5 and looked at
>>>>>>> the stat.txt, I can only see the entries in 
>>>>>>> system.cpu.iq.FU_type_0::FloatAdd,
>>>>>>> where as the entries in FloatMul and FloatDiv remains 0.
>>>>>>>
>>>>>>> If I understand correctly, these stats refer to the micro-ops. Does
>>>>>>> that mean the MULSS and DIVSS instruction are broken down and executed 
>>>>>>> with
>>>>>>> floating point Add?
>>>>>>>
>>>>>>> Thanks
>>>>>>>
>>>>>>>
>>>>>>> ___
>>>>>>> gem5-users mailing list
>>>>>>> gem5-users@gem5.org
>>>>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>>>>>
>>>>>>
>>>>>>
>>>>>
>>>>> ___
>>>>> gem5-users mailing list
>>>>> gem5-users@gem5.org
>>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>>>
>>>>
>>>> ___
>>>> gem5-users mailing list
>>>> gem5-users@gem5.org
>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>>
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] x86 floating point instruction

2018-05-25 Thread Tariq Azmy
Hi Gabe, Jason,

Are those x86 SIMD SSE arithmetic instructions take only one cycle as
latency? I looked into the FuncUnitConfig.py and seems like the op lats for
the SIMD functional units are not defined, so I assumed it takes value of 1
by default.

I am not really familiar with x86 SIMD extension, so maybe this question is
more related to x86 ISA in general.

Thanks.

On Thu, May 24, 2018 at 9:52 AM, Jason Lowe-Power <ja...@lowepower.com>
wrote:

> Hi Tariq,
>
> It wold be great if you could review Gabe's patch on gerrit. Since it
> works for you, giving it a +1 or a +2 would be appropriate.
>
> Cheers,
> Jason
>
> On Wed, May 23, 2018 at 5:56 PM Tariq Azmy <tariqslaye...@gmail.com>
> wrote:
>
>> Thanks Gabe. Yeah it does not impact the program but it's just that the
>> statistic is incorrect.
>>
>> By the way, I applied the patch and stats now shows correct micro-ops
>> entries.
>>
>> Appreciate your help. Thanks again
>>
>> On Wed, May 23, 2018 at 6:51 PM, Gabe Black <gabebl...@google.com> wrote:
>>
>>> Yep, those microops aren't given a operand class, and so the isa parser
>>> is guessing and making the FloatAddOp. I haven't really tested this beyond
>>> making sure it compiles, but here's a patch that might get this working for
>>> you.
>>>
>>> https://gem5-review.googlesource.com/c/public/gem5/+/10541
>>>
>>> Gabe
>>>
>>> On Wed, May 23, 2018 at 4:13 PM, Gabe Black <gabebl...@google.com>
>>> wrote:
>>>
>>>> I'm confident they aren't implemented with floating point add. It's
>>>> likely either that the microops are misclassified, or they're unimplemented
>>>> and printing a warning, but the fact that they don't actually do any math
>>>> isn't impacting your program for whatever reason. I'll take a quick look.
>>>>
>>>> Gabe
>>>>
>>>> On Wed, May 23, 2018 at 2:07 PM, Tariq Azmy <tariqslaye...@gmail.com>
>>>> wrote:
>>>>
>>>>> Hi,
>>>>>
>>>>> I wrote simple code that does simple floating point multiplication and
>>>>> division operation and from the assembly, I can see there are MULSS and
>>>>> DIVSS instructions. But after I ran the simulation on gem5 and looked at
>>>>> the stat.txt, I can only see the entries in 
>>>>> system.cpu.iq.FU_type_0::FloatAdd,
>>>>> where as the entries in FloatMul and FloatDiv remains 0.
>>>>>
>>>>> If I understand correctly, these stats refer to the micro-ops. Does
>>>>> that mean the MULSS and DIVSS instruction are broken down and executed 
>>>>> with
>>>>> floating point Add?
>>>>>
>>>>> Thanks
>>>>>
>>>>>
>>>>> ___
>>>>> gem5-users mailing list
>>>>> gem5-users@gem5.org
>>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>>>
>>>>
>>>>
>>>
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] x86 floating point instruction

2018-05-23 Thread Tariq Azmy
Thanks Gabe. Yeah it does not impact the program but it's just that the
statistic is incorrect.

By the way, I applied the patch and stats now shows correct micro-ops
entries.

Appreciate your help. Thanks again

On Wed, May 23, 2018 at 6:51 PM, Gabe Black <gabebl...@google.com> wrote:

> Yep, those microops aren't given a operand class, and so the isa parser is
> guessing and making the FloatAddOp. I haven't really tested this beyond
> making sure it compiles, but here's a patch that might get this working for
> you.
>
> https://gem5-review.googlesource.com/c/public/gem5/+/10541
>
> Gabe
>
> On Wed, May 23, 2018 at 4:13 PM, Gabe Black <gabebl...@google.com> wrote:
>
>> I'm confident they aren't implemented with floating point add. It's
>> likely either that the microops are misclassified, or they're unimplemented
>> and printing a warning, but the fact that they don't actually do any math
>> isn't impacting your program for whatever reason. I'll take a quick look.
>>
>> Gabe
>>
>> On Wed, May 23, 2018 at 2:07 PM, Tariq Azmy <tariqslaye...@gmail.com>
>> wrote:
>>
>>> Hi,
>>>
>>> I wrote simple code that does simple floating point multiplication and
>>> division operation and from the assembly, I can see there are MULSS and
>>> DIVSS instructions. But after I ran the simulation on gem5 and looked at
>>> the stat.txt, I can only see the entries in 
>>> system.cpu.iq.FU_type_0::FloatAdd,
>>> where as the entries in FloatMul and FloatDiv remains 0.
>>>
>>> If I understand correctly, these stats refer to the micro-ops. Does that
>>> mean the MULSS and DIVSS instruction are broken down and executed with
>>> floating point Add?
>>>
>>> Thanks
>>>
>>>
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>
>>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] x86 floating point instruction

2018-05-23 Thread Tariq Azmy
Hi,

I wrote simple code that does simple floating point multiplication and
division operation and from the assembly, I can see there are MULSS and
DIVSS instructions. But after I ran the simulation on gem5 and looked at
the stat.txt, I can only see the entries in
system.cpu.iq.FU_type_0::FloatAdd, where as the entries in FloatMul and
FloatDiv remains 0.

If I understand correctly, these stats refer to the micro-ops. Does that
mean the MULSS and DIVSS instruction are broken down and executed with
floating point Add?

Thanks
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] enum header file

2018-05-11 Thread Tariq Azmy
Some of cpu source codes include header files that begin with enum/.. such
as:

#include "enums/OpClass.hh"
#include "enums/StaticInstFlags.hh"

Where are these sources located so that I can see 'em?

Thanks
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Running PARSEC Benchmark in SE Mode

2018-04-24 Thread Tariq Azmy
Hi all,

There is a wiki page that describes how to run PARSEC benchmark on gem5,
but it is built to run in FS mode. I wonder if anyone has tried running
those benchmarks in SE mode?

Thanks.
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Adding a new resource

2018-03-17 Thread Tariq Azmy
By "resources", I assume you are referring to each of the stage in the
out-of-order pipeline? Those stages' implementation codes (fetch, decode,
rename, etc..) are located inside the cpu/o3 directory. Branch prediction
typically is done in fetch stage, so if you look inside the fetch.hh source
code, it includes the header file of "cpu/pred/bpred_unit.hh". So if go up
one level, to the cpu/pred directory, that is where the branch predictor
implementation code is located.

As far as value predictor, I am not sure how you are going to implement it,
but it probably needs to work with or link to other stages/resources such
as iew, instruction queue, rob..

Hope this helps.

On Sat, Mar 17, 2018 at 3:44 PM, Pawan Joshi 
wrote:

> Okay, that makes sense. But isn't there a separate "resources" directory
> where I can see stuff like branch predictors implemented? I don't have any
> br. pred. in my current cpu/o3 directory.
> I wanted that as I can get a template to work with.
>
>
> Pawan
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users