Hi Gabe:
I wonder the reason that add a “const” to “code("
${{cls.cxx_type}} create() const;")” in src/python/m5/SimObject.py?
Because the patch modified the src/dev/pci/device.cc, add a
PciBarNoneParams::create() with const:
“PciBarNoneParams::create() const
{
return new PciBarNone(*this);
}”
[cid:image001.png@01D6B5C7.A9C99C90]
________________________________
李翼超（Charlie）
华为技术有限公司 Huawei Technologies Co., Ltd.
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发件人: Gabe Black via gem5-users [mailto:gem5-users@gem5.org]
发送时间: 2020年11月7日 22:42
收件人: gem5 users mailing list <gem5-users@gem5.org>
抄送: Gabe Black <gabe.bl...@gmail.com>
主题: [gem5-users] Re: Ethernet support for ARM FS simulation
The way create methods and constructors were set up was standardized and
largely automated recently. If you're backporting a change across when that
happened, you're going to have to adjust those so they work with the old, less
consistent versions, but it should be very straightforward (turning references
into pointers mostly).
Gabe
On Fri, Nov 6, 2020 at 2:53 AM Liyichao
<liyic...@huawei.com<mailto:liyic...@huawei.com>> wrote:
Hi Gabe:
I use your patch to fix my GEM5 20.0.0.3, but somethins wrong in compilation:
[SO PARAM] EtherDevBase -> ARM/params/EtherDevBase.hh
[ CXX] ARM/dev/virtio/pci.cc -> .o
[SO PARAM] EtherDevice -> ARM/params/EtherDevice.hh
[SO PARAM] EtherTap -> ARM/params/EtherTap.hh
[SO PARAM] EtherTapStub -> ARM/params/EtherTapStub.hh
[SO PARAM] DistEtherLink -> ARM/params/DistEtherLink.hh
[SO PARAM] IGbE -> ARM/params/IGbE.hh
[SO PARAM] NSGigE -> ARM/params/NSGigE.hh
[SO PARAM] Sinic -> ARM/params/Sinic.hh
[SO PARAM] IdeController -> ARM/params/IdeController.hh
[SO PARAM] IdeDisk -> ARM/params/IdeDisk.hh
[ENUM STR] ArmPciIntRouting, True -> ARM/enums/ArmPciIntRouting.cc
[ENUM STR] IdeID, True -> ARM/enums/IdeID.cc
[SO PyBind] A9GlobalTimer -> ARM/python/_m5/param_A9GlobalTimer.cc
[SO PyBind] A9SCU -> ARM/python/_m5/param_A9SCU.cc
[SO PyBind] AmbaDmaDevice -> ARM/python/_m5/param_AmbaDmaDevice.cc
[SO PyBind] AmbaFake -> ARM/python/_m5/param_AmbaFake.cc
[SO PyBind] AmbaIntDevice -> ARM/python/_m5/param_AmbaIntDevice.cc
[SO PyBind] AmbaPioDevice -> ARM/python/_m5/param_AmbaPioDevice.cc
[SO PyBind] CopyEngine -> ARM/python/_m5/param_CopyEngine.cc
[SO PyBind] CpuLocalTimer -> ARM/python/_m5/param_CpuLocalTimer.cc
In file included from build/ARM/dev/virtio/pci.hh:43:0,
from build/ARM/dev/virtio/pci.cc:38:
build/ARM/dev/pci/device.hh: In constructor 'PciBar::PciBar(const
PciBarParams&)':
build/ARM/dev/pci/device.hh:74:48: error: no matching function for call to
'SimObject::SimObject(const PciBarParams&)'
PciBar(const PciBarParams &p) : SimObject(p) {}
^
In file included from build/ARM/dev/virtio/base.hh:46:0,
from build/ARM/dev/virtio/pci.hh:42,
from build/ARM/dev/virtio/pci.cc:38:
build/ARM/sim/sim_object.hh:120:5: note: candidate: SimObject::SimObject(const
Params*)
SimObject(const Params *_params);
^~~~~~~~~
build/ARM/sim/sim_object.hh:120:5: note: no known conversion for argument 1
from 'const PciBarParams' to 'const Params* {aka const SimObjectParams*}'
[SO PyBind] DistEtherLink -> ARM/python/_m5/param_DistEtherLink.cc
[SO PyBind] EtherBus -> ARM/python/_m5/param_EtherBus.cc
[SO PyBind] EtherDevBase -> ARM/python/_m5/param_EtherDevBase.cc
[SO PyBind] EtherDevice -> ARM/python/_m5/param_EtherDevice.cc
[SO PyBind] EtherDump -> ARM/python/_m5/param_EtherDump.cc
[SO PyBind] EtherLink -> ARM/python/_m5/param_EtherLink.cc
[SO PyBind] EtherSwitch -> ARM/python/_m5/param_EtherSwitch.cc
[SO PyBind] EtherTap -> ARM/python/_m5/param_EtherTap.cc
[SO PyBind] EtherTapBase -> ARM/python/_m5/param_EtherTapBase.cc
[SO PyBind] EtherTapStub -> ARM/python/_m5/param_EtherTapStub.cc
[SO PyBind] FVPBasePwrCtrl -> ARM/python/_m5/param_FVPBasePwrCtrl.cc
[SO PyBind] GenericArmPciHost -> ARM/python/_m5/param_GenericArmPciHost.cc
[SO PyBind] HDLcd -> ARM/python/_m5/param_HDLcd.cc
[SO PyBind] IGbE -> ARM/python/_m5/param_IGbE.cc
[SO PyBind] IdeController -> ARM/python/_m5/param_IdeController.cc
[SO PyBind] IdeDisk -> ARM/python/_m5/param_IdeDisk.cc
[SO PyBind] NSGigE -> ARM/python/_m5/param_NSGigE.cc
scons: *** [build/ARM/dev/virtio/pci.o] Error 1
scons: building terminated because of errors.
*** Summary of Warnings ***
Warning: Your compiler doesn't support incremental linking and lto at the same
time, so lto is being disabled. To force lto on anyway, use the --force-lto
option. That will
disable partial linking.
Warning: While checking protoc version: [Errno 2] No such file or directory
root@ubuntu-kunpeng920-1:/home/l00515693/gem5_repo/gem5# vim
build/ARM/dev/pci/device.hh
root@ubuntu-kunpeng920-1:/home/l00515693/gem5_repo/gem5# vim
build/ARM/dev/pci/device.hh
________________________________
李翼超（Charlie）
华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手 机：15858232899
电子邮件：liyic...@huawei.com<mailto:liyic...@huawei.com>
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]
________________________________
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止任何其他人以任何形式使用（包括但不限于全部或部分地泄露、复制、或散发）本邮件中
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发件人: Gabe Black [mailto:gabe.bl...@gmail.com<mailto:gabe.bl...@gmail.com>]
发送时间: 2020年11月5日 21:19
收件人: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
抄送: Liyichao <liyic...@huawei.com<mailto:liyic...@huawei.com>>
主题: Re: [gem5-users] Re: Ethernet support for ARM FS simulation
That sounds like the problem I fixed with this CL:
https://gem5-review.googlesource.com/c/public/gem5/+/35516
Gabe
On Thu, Nov 5, 2020 at 4:42 AM Liyichao via gem5-users
<gem5-users@gem5.org<mailto:gem5-users@gem5.org>> wrote:
Hi Gabe:
I have looked at the email below, I also has the same question. As you
mentioned, I just modified the FSConfig.py in function makeArmSystem with
“self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
InterruptLine=1, InterruptPin=1)
pci_devices.append(self.ethernet)” without any modifications in src/***
and use the latest img and kernel from GEM5 WEBSITE, but when I use
fs.py to bootup , there is a fatal print “fatal: Unable to find destination for
[0x40000008:0x4000000c] on system.iobus”.
My cmd is:
./build/ARM/gem5.opt
--debug-flags=AddrRanges,NoncoherentXBar,DMA,EthernetEEPROM,Ethernet
configs/example/fs.py --cpu-type=ArmV8KvmCPU --kernel=vmlinux -n 1
--machine-type=VExpress_GEM5_V1
--disk-image=expanded-aarch64-ubuntu-trusty-headless.img --cpu-clock=2.6GHz
--mem-type=DDR4_2933_16x4_new --mem-size=8GB
My GEM5 VERSION is 20.0.0.3
You shouldn't modify your config by changing anything in src/, you should
do that in the config scripts. If you want to add additional devices, they
don't have to be part of the platform object, they just need to be
connected to the right busses, etc.
Gabe
On Fri, Aug 28, 2020 at 12:06 PM HENG ZHUO via gem5-users <
gem5-users@gem5.org<mailto:gem5-users@gem5.org>> wrote:
> Hi all,
>
> I noticed with the recent updates in ARM ISA support, now default machine
> setup is using VExpress_GEM5_V1, which is great, with the 2019 build kernel
> and boot loadert tested and everything. However, I also know that
> VExpress_GEM5 does not support ethernet device. What would be best setup if
> I want to use ethernet device, but with newer built kernel setup?
>
> 1) Shall I add ethernet device to VExpress_GEM5 machine config? This
> should be most ideal case, in terms of simulated system. Assuming I can add
> a new device in the src/dev/arm/RealView.py under VExpress_GEM5_V1. But,
> the dtb is auto generated, seems like I also need to add entry in the
> auto-generated device tree, anyone has any directions on how to add new
> devices in this scenario?
>
> 2) Can I use the old VExpress_EMM64 machine, but with newer build 2019
> kernel and boatload, my guess is not, I would assume the kernel is
> customized based on the machine VExpress_GEM5.
>
> 3) Stick with using older build (2018 build kernel and bootloader), with
> machine VExpress_EMM64. This should be working by default, but losing the
> ability to use more updated kernel and machine config.
>
> Any suggestions, insights would be appreciated!
>
> Best,
> Heng
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_______________________________________________
________________________________
李翼超（Charlie）
华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手 机：15858232899
电子邮件：liyic...@huawei.com<mailto:liyic...@huawei.com>
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]
________________________________
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