[gem5-users] CHi - assertion error when modelling "mostly inclusive" for private L2$

[Javed Osmany via gem5-users]

Hello

I am simulating a multicore Ruby system using CHI, using the Parsec/Splash2 
benchmarks & gem5-21.2.1.0.
It consists of three clusters :

1)      Little cluster of 4 CPUs, each CPU has private L1$ and L2$

2)      Middle cluster of 3 CPUs, each CPU has private L1$ and L2$

3)      Big cluster of 1 CPU with private L1$ and L2$.

By default, the L2$ and L3$ (residing in the HNF) have their clusivity set to 
strict_inclusive and mostly_inclusive respectively (CHI_config.py):

class CHI_L2Controller(CHI_Cache_Controller):
    '''
    Default parameters for a L2 Cache controller
    '''

    def __init__(self, ruby_system, cache, l2_clusivity, prefetcher):
        super(CHI_L2Controller, self).__init__(ruby_system)
        self.sequencer = NULL
        self.cache = cache
        self.use_prefetcher = False
        self.allow_SD = True
        self.is_HN = False
        self.enable_DMT = False
        self.enable_DCT = False
        self.send_evictions = False
        # Strict inclusive MOESI
         self.alloc_on_seq_acc = False
         self.alloc_on_seq_line_write = False
         self.alloc_on_readshared = True
         self.alloc_on_readunique = True
         self.alloc_on_readonce = True
         self.alloc_on_writeback = True
         self.dealloc_on_unique = False
         self.dealloc_on_shared = False
         self.dealloc_backinv_unique = True
         self.dealloc_backinv_shared = True

class CHI_HNFController(CHI_Cache_Controller):
    '''
    Default parameters for a coherent home node (HNF) cache controller
    '''

    #def __init__(self, ruby_system, cache, prefetcher, addr_ranges):
    def __init__(self, ruby_system, cache, prefetcher, addr_ranges, 
hnf_enable_dmt, hnf_enable_dct, \
                 num_tbe, num_repl_tbe, num_snp_tbe, unified_repl_tbe, 
l3_clusivity):
        super(CHI_HNFController, self).__init__(ruby_system)
        self.sequencer = NULL
        self.cache = cache
        self.use_prefetcher = False
        self.addr_ranges = addr_ranges
        self.allow_SD = True
        self.is_HN = True
        #self.enable_DMT = True
        #self.enable_DCT = True
        self.enable_DMT = hnf_enable_dmt
        self.enable_DCT = hnf_enable_dct
        self.send_evictions = False
        # MOESI / Mostly inclusive for shared / Exclusive for unique
        self.alloc_on_seq_acc = False
        self.alloc_on_seq_line_write = False
        self.alloc_on_readshared = True
        self.alloc_on_readunique = False
        self.alloc_on_readonce = True
        self.alloc_on_writeback = True
        self.dealloc_on_unique = True
        self.dealloc_on_shared = False
        self.dealloc_backinv_unique = False
        self.dealloc_backinv_shared = False

The simulations complete okay for the default clusivity of L2$ and L3$.
However, if I change the L2$ clusivity to "mostly_inclusive" some of the 
benchmarks are failing with an assertion error.

I took the default L3$ clusivity of mostly_inclusive to update the L2$ 
clusivity to be mostly_inclusive:

class CHI_L2Controller(CHI_Cache_Controller):
    '''
    Default parameters for a L2 Cache controller
    '''

    def __init__(self, ruby_system, cache, l2_clusivity, prefetcher):
        super(CHI_L2Controller, self).__init__(ruby_system)
        self.sequencer = NULL
        self.cache = cache
        self.use_prefetcher = False
        self.allow_SD = True
        self.is_HN = False
        self.enable_DMT = False
        self.enable_DCT = False
        self.send_evictions = False
        # Strict inclusive MOESI
        if (l2_clusivity == "sincl"):
            self.alloc_on_seq_acc = False
            self.alloc_on_seq_line_write = False
            self.alloc_on_readshared = True
            self.alloc_on_readunique = True
            self.alloc_on_readonce = True
            self.alloc_on_writeback = True
            self.dealloc_on_unique = False
            self.dealloc_on_shared = False
            self.dealloc_backinv_unique = True
            self.dealloc_backinv_shared = True
        elif (l2_clusivity == "mincl"):
            # Mostly inclusive MOESI
            self.alloc_on_seq_acc = False
            self.alloc_on_seq_line_write = False
            self.alloc_on_readshared = True
            self.alloc_on_readunique = False
            self.alloc_on_readonce = True
            self.alloc_on_writeback = True
            self.dealloc_on_unique = True
            self.dealloc_on_shared = False
            self.dealloc_backinv_unique = False
            self.dealloc_backinv_shared = False

The assertion error being:

log_parsec_volrend_134_8rnf_1snf_4hnf_3_clust_all_priv_l2.txt:build/ARM/mem/ruby/protocol/Cache_Controller.cc:5477:
 panic: Runtime Error at CHI-cache-actions.sm:1947: assert failure.

QS 1: Even though the L2$ is private, i am assuming that L2$ clusivity can be 
set to mostly_inclusive. Is that assumption correct?
QS2: If the answer to QS 1 is yes, then it would seem that the 
"mostly_inclusive" settings for the L2$ (copied from the mostly_inclusive 
settings for L3$ residing in the HNF) could be the root cause of the problem. 
Any thoughts on this ?

Thanks in advance
JO


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