Re: [gem5-users] Memory models possibilities

2018-06-01 Thread Jason Lowe-Power
Hi Rich,

Some answers inline below.

Cheers,
Jason

On Tue, May 29, 2018 at 4:59 PM Richard Brown 
wrote:

> Hello everyone,
>
> I have been reading several posts in this forum and the gem5
> documentation, I am new with gem5, I  have to work with memory subsystem
> and I have already changed characteristics on main memory and cache memory
> as train. However I have some questions that I have not answered reading
> the forum:
>
> 1. gem5 has two memory models, i.e. classic and ruby. I need to change the
> read and write latencies, to be asymmetric for modeling an NVM memory. I
> know it is super easy in the classic model, but I also need to change the
> coherence protocol to avoid writes in some cache level, i.e the LLC is
> supposed to be an NVM so I do not want to always write on it.
>
> Is it possible to have asymmetric latencies with Ruby model? I tried it,
> but I got an error when I simulate in full-system mode, I added asymmetric
> latencies and stall the execution if the bank is busy, but many stalls
> caused an error. In classic model I do not have problems but the cache
> manage is fixed, I think it is a mess to change the cache manage to avoid
> writes in one level.
>
> This should be straightforward. For caches, you can simply change the
latencies used when enqueuing messages (e.g.,
https://gem5.googlesource.com/public/gem5/+/master/src/mem/protocol/MESI_Two_Level-L1cache.sm#526
).
If you're talking about the DRAMCtrl that might be a little harder. If
you're trying to use a new memory technology as your main-memory you might
want to write a new model (or use something like NVMain).


> 2. I need to access cache line, I need to count the modified bits. Is it
> possible to access cache line in both memory models?
>

Yes, it should be. It might not be super easy, but you should be able to do
this in either the classic caches or in Ruby.


>
> 3. I have read papers where people use NVMain with gem5, is possible to
> use it as cache memory only for LLC? L1 and L2 will be SRAM.
>

There isn't an easy way to use NVMain as a cache. You'll likely need to
re-write the cache model to get something like this to work. Which, if
you're going to be deeply changing the cache models, you'll likely have
more luck using Ruby than the classic caches.


>
> 4. I have read some posts where people talk about an unified memory model
> for gem5, are there people working on it?
>

Unified how? Between Ruby and classic? That won't happen anytime soon.
There's a unified memory between the CPU and GPU, though...


>
> Thanks in advance for any help.
>
> --
> All the best
>Rich
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[gem5-users] Memory models possibilities

2018-05-29 Thread Richard Brown
Hello everyone,

I have been reading several posts in this forum and the gem5 documentation,
I am new with gem5, I  have to work with memory subsystem and I have
already changed characteristics on main memory and cache memory as train.
However I have some questions that I have not answered reading the forum:

1. gem5 has two memory models, i.e. classic and ruby. I need to change the
read and write latencies, to be asymmetric for modeling an NVM memory. I
know it is super easy in the classic model, but I also need to change the
coherence protocol to avoid writes in some cache level, i.e the LLC is
supposed to be an NVM so I do not want to always write on it.

Is it possible to have asymmetric latencies with Ruby model? I tried it,
but I got an error when I simulate in full-system mode, I added asymmetric
latencies and stall the execution if the bank is busy, but many stalls
caused an error. In classic model I do not have problems but the cache
manage is fixed, I think it is a mess to change the cache manage to avoid
writes in one level.

2. I need to access cache line, I need to count the modified bits. Is it
possible to access cache line in both memory models?

3. I have read papers where people use NVMain with gem5, is possible to use
it as cache memory only for LLC? L1 and L2 will be SRAM.

4. I have read some posts where people talk about an unified memory model
for gem5, are there people working on it?

Thanks in advance for any help.

--
All the best
   Rich
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