This is a complex question. CHI is an ARM protocol which obviously work for ARM
ISA's... At least. Does it work for x86? There are good chances that the answer
is "yes" because x86 memory model is more restrictive than ARM's. If you need
an assertive answer though, I can't give it to you. This
Thanks, that's great!
I just have a follow-up question: Can we have CHI for X86? I compiled gem5
for X86_CHI, and it was compiled successfully. However, I was wondering if
it would be working correctly in terms of functionality and for longer
runs?
On Fri, Jul 16, 2021 at 10:26 AM Gabriel Busnot
Indeed, only MESI_two_level's L1 cache has a prefetcher, my bad. From here,
your two only options to get an L2 prefetcher is either to use MESI_two_level
or to add prefetcher support to MESI_three_level's L1 cache, which will not be
an easy job, I think.
CHI, which is a MOESI implementation,
Thanks for the reply!
I'm using MESI_Threee_Level. I checked both develop and stable branches.
Based n what I see, only one prefetcher is created at this line
https://github.com/gem5/gem5/blob/eb919229e63c4daa208a1d9e4856755c1e914154/configs/ruby/MESI_Three_Level.py#L129
Also, by looking at the
Hi Majid,
Which protocol are you using?
With MESI_Two_Level and MESI_Three_Level, the L1 cache has an "enable_prefetch"
boolean parameter, juste like the L0.
You can then customize the prefetcher of each cache according to the options
available in RubyPrefetcher.py.
Best,
Gabriel
