[gem5-users] Re: FLUSH request from CPU sequencer to cache controller

2020-10-06 Thread Daecheol You via gem5-users
Thanks Jason, Could you explain what other things should be considered for FLUSH if invalidate and write-back is not enough? Or is it fine modifying the CPU sequencer that it just ignores the FLUSH request? ___ gem5-users mailing list -- gem5-users@gem5.

[gem5-users] Re: FLUSH request from CPU sequencer to cache controller

2020-10-06 Thread Jason Lowe-Power via gem5-users
Hi Daecheol, The complication comes from handling all of the corner cases. What happens if you get a flush for a line when you've sent a request but haven't received a response? What about when you've received an invalidation, but you haven't responded yet? There are many intermediate states that

[gem5-users] Re: FLUSH request from CPU sequencer to cache controller

2020-10-05 Thread Jason Lowe-Power via gem5-users
Hi Daecheol, Unfortunately, the flush command is a bit more complicated to implement than just a simple replacement. I responded to another message about this on the mailing list a few minutes ago that you can see for more information. Cheers, Jason On Mon, Sep 28, 2020 at 8:59 PM Daecheol You v