Hi Yujiecui,

The fetch stage in O3CPU fetches cache lines from instruction cache and
also calls ISA specific decoder implementation to decode the raw bytes into
instructions and access the corresponding micro-ops for these instructions
(In other words, fetch stage outputs the micrco-ops). That's why you are
seeing all these decode calls. As far as I understand (specifically for
x86),  the functions you are referring to will decode a machine instruction
corresponding to the given PC, check if the instruction exist across the
cache block boundary and fetch more bytes (i.e. next cache block) etc.  As
far as Rom is concerned, I think it holds the micro-ops.

I will suggest you have a look at the following page:

http://www.m5sim.org/X86_Instruction_decoding

and decoder implementation for some ISA e.g. src/arch/x86/decoder.hh

-Ayaz

On Tue, Nov 3, 2020 at 4:52 AM yujiecui--- via gem5-users <
gem5-users@gem5.org> wrote:

> In the fetch function in the src/cpu/O3/fetch.impl file, when fetching
> instructions to the fetch queue, I saw some operations on the decoder,
> which made me very confused. For example, decoder[tid]->decode(thisPC),
> decoder[tid]->instReady(), decoder[tid]->needMoreBytes(),
> decoder[tid]->moreBytes(thisPC, fetchAddr, inst). Why are there so many
> decoding operations when fetching instructions into the fetch queue? What
> is the role of decoder[tid] here? What does needMoreBytes() do?
>
> Still fetch function in the src/cpu/O3/fetch.impl file, I saw some
> RomMicroPC. I want to know what kind of instructions are in rom?
>
> I stepped through it many times, but I still have trouble understanding.
> All related answers are very welcome. Thanks
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