Thanks Ali.
I have recompiled with the “for()” instruction implemented in the “decoder.isa”
file for SPARC Arch. Apparently now “456.hmmer” is running.
I may have to do this in the hard way by implementing the instructions missing
until I find another suitable ISA (like RISC-V which I believe Al
Hi Monir,
As Jason mentioned this happens (on all ISAs) because of an unimplemented
instruction. If you look at arch/sparc/isa/decoder.isa you’ll find a line like
FailUnimp::for(). What is missing here is the implementation of the for
instruction. You should be able to find a definition for it
Hi Monir,
No, I don't have any good suggestions for you. Too bad you're not inside
ARM. I bet they have something internally ;) (note: I have no knowledge of
what ARM may or may not be doing internally).
Another (semi-)sarcastic response: It may be less effort to add the RISC-V
ISA to gem5 than t
Thanks Jason. You are right, too many times the struggle is with the ISA of
choice in my case.
But, I need something which I can model in GEM5 and also have synthesizable RTL
available to play with. Any idea?
/Monir
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Hi Monir,
I won't belabor the point about using a better supported ISA this time :).
For your other options, I definitely wouldn't change the instruction to a
warning. That may be appropriate for a few instructions, like prefetch, but
it's inappropriate for most. I don't know the SPARC ISA off the
Hello All,
I was running the “456.hmmer” from the SPEC benchmark Suite, which was compiled
by the “linux-gcc-sparc” compiler available from the Gem5 website. I did
successfully run the “bzip” and “mcf” benchmarks, but while running “hmmer” I
ran into error below (I used the script described in M
