Yes, that is how it would work. fs.py and Benchmarks.py are included in the
configs/ directory of the m5 tree.
Lisa
On Tue, Mar 15, 2011 at 9:32 AM, Adwait Jog adwait...@gmail.com wrote:
If I cross-compile SPEC 2006 benchmarks and put binaries in the disk,
should I will be able to run SPEC
I just noticed this string of emails, and coincidentally I just posted all
of Vince's patches to the Review Board except one (the last) which had been
addressed in another changeset. I'd been using them for a little bit Vince
to get some 2k6 workloads going, but not all of 2k6 works but they
Hi Takaaki,
I notice you are using m5-stable, I suggest using the development repository
as it is much more up to date. In practice, the stable repository doesn't
get updated as much as it should and generally the dev repository is
better. Let us know if you still have problems with that tree.
At first blush, it appears your main problem is that you are checkpointing
and restoring different runs.
When you checkpoint something, it's like saving the state so that when you
restore, it's like you never checkpointed at all and just continue
running...in your case, you've checkpointed a run
It looks to me like you've done exactly what you wanted...before insertion
is one ordering of MRU (block 0) to LRU (block 7) and then after insertion
the block that was LRU is now MRU and the rest are shifted down one block.
Is that not the behavior you were looking for?
Lisa
On Wed, Nov 10,
Hi Sunitha,
I suspect your problem is because you're making your L2 cache out of a
BaseCache object. The presumption I think is that BaseCache is a base
class, and child classes like L1Cache inherit from it so that they can be
parameterized appropriately to their level. More to the point,
The contextId in a request corresponds to the CPU/context that generated the
request.
Lisa
On Tue, Sep 7, 2010 at 4:15 PM, Malek Musleh malek.mus...@gmail.com wrote:
Hello,
I have a question in regards to the context ID field of the pkt-req
with use of selective statistics update.
If I
Hi Lide,
There isn't a direct way to access the caches from the CPU right now...this
is a design decision to keep M5 modular - all the CPU knows is what is
attached to its ports, that way you can have completely arbitrary
hierarchies and topologies without any dependencies in the CPU code as to
?
Lide
On Wed, Jul 14, 2010 at 12:11 PM, Lisa Hsu h...@eecs.umich.edu wrote:
Hi Lide,
There isn't a direct way to access the caches from the CPU right
now...this is a design decision to keep M5 modular - all the CPU knows is
what is attached to its ports, that way you can have completely
Hi Matt,
As far as I know, no one has touched m5threads in a long time. I don't think
there is any documentation aside from the README either, aside from any
comments you might find in the code or discussions that might be on the
mailing list archive.
Lisa
On Mon, Jun 28, 2010 at 10:03 AM,
Hi Susie,
The code for that has been checked into the development repository. It's in
the util/ directory and is called checkpoint-aggregator.py.
Lisa
On Sun, Jun 20, 2010 at 3:27 PM, Susie Sally ss758...@gmail.com wrote:
Hi,
I would like to run simulations with multiple workloads with
Hi Malek,
Building from builder.cc implies deriving from Cache, which derives from
BaseCache. The TagStores are implicit to CacheTagStore but are not a part
of BaseCache. Do you not want a tag-store policy associated with your
cache?
Lisa
On Thu, Jun 10, 2010 at 1:22 PM, Malek Musleh
Hi Sheng,
Try using the cleanupRefs() function in the cache tags implementation you
are using. This function is called back at the end of simulation and you
can have it walk through the cache blocks and do whatever you like,
including increment/decrement statistics.
Lisa
On Thu, Jun 3, 2010 at
Maybe Korey can correct me if I'm wrong, but I think max_insts_all_threads
says that each thread within an SMT processor must hit N insts, but doesn't
apply across multiple cpus. There was a thread in the last month or so with
advice on how to make all cpus go to a certain limit, see link.
see our repositories:
http://repo.m5sim.org/
http://repo.m5sim.org/I don't know that the m5thread library has been used
very vigorously so there may be some wrinkles, but it's the only one
available that we know of.
Lisa
On Wed, Apr 14, 2010 at 12:56 PM, Eberle rambo.u...@gmail.com wrote:
You have two choices, the first of which is not general. If you are looking
at writebacks from private caches that are associated only with a single
core, then you can infer the core IDs of the writebacks based on which cache
it came from (but not the PC). This is not generalizeable if the
Hi Sujay,
I don't think there's any way to keep a stat from being reset when reset()
is called, sorry. You'd have to hack that in.
Lisa
On Wed, Mar 17, 2010 at 2:57 PM, Sujay Phadke spha...@eecs.umich.eduwrote:
Hello,
If I have an occupancy stat declared as an average. This is
Veydan,
the clock you are talking about refers to the global system clock. The CPU
clock setting that you noticed in fs.py is the CPU clock. The global system
clock is fast so that you can have clocks of other components in the system
(busses, etc.) set relative to the global clock at a fine
Soumyaroop,
I have a patch in my tree which does something similar. I am cleaning it up
now for public distribution, but even then it won't be totally tested,
particularly on anything but ALPHA. Can you wait until I push it? You can
use it as a reference point to modify for SMT. Currently,
Generally M5 is run in a linux/unix environment. If you want to run on a
windows platform, you'd have to install cygwin and run it under that. I
know Steve has some experience with this, but the general practice is to use
a *nix machine.
Lisa
On Thu, Dec 24, 2009 at 10:54 AM, Uthaiwan
What is the reason it has to be a single run? It would be much easier to
just do two runs, one with private, one with shared.
Lisa
On Thu, Dec 3, 2009 at 7:34 AM, Kenzo Van Craeynest
kenzo.vancraeyn...@elis.ugent.be wrote:
Hi
In a multicore configuration, is there a way to duplicate the l2
?
Thanks,
Amir
On Fri, Nov 20, 2009 at 4:54 PM, Lisa Hsu h...@eecs.umich.edu wrote:
Since you're running full system, it's probably because those processors
are in an idle loop. Check the user/kernel time stats. However, why 5/8
would be high is unclear, I don't know why the last 3 wouldnt
Junli,
Note that the wiki page describing using linux-dist has this caveat:
Note that this process is quite deprecated and not well supported. We
suggest that you get your disk images either from the downloads page, or if
that doesn't satisfy your needs, with a Gentoo stage 3 image. While we're
Junli,
Note that the disk image and the linux binary are completely distinct. The
linux binary does not reside on the disk image. I am not sure what version
of linux is in that tar, it might be 2.4.* or so. If you want MPICH to
work, that binary will have to go on the disk image.
Lisa
Try using the full path to the mpiexec command.
Lisa
2009/11/16 junli gu guju...@gmail.com
Hi everyone:
My simulator can run non-MPI programs successfully.
I am trying to run MPI programs on fullsystem mode. I have done he
following steps:
1.install MPICH on the disk image binded with
I'm not sure about #2, but for #1 you could do either.
If you have an existing disk image that works, you could just mount the
image and add your binaries (along with any shared libraries it might need
but are not already on the image) to it, or you could make your own, which
is also fine. To
Simpoints are an intrinsic feature of workloads - if you want to take a
checkpoint at a simpoint, you must do --take-checkpoint 0 --simpoint, as
described in our asplos tutorial. If you look in cpu2000.py, the simpoint
parameters are part of each benchmark.
Lisa
On Fri, Aug 7, 2009 at 3:12 PM,
If you know what tick the benchmark starts at, just don't begin your
traceflagging until that point (i.e. --trace-start=Tick)
Lisa
On Mon, Aug 3, 2009 at 9:22 AM, Sujay Phadke spha...@eecs.umich.edu wrote:
Hello,
I am trying to collect memory traces running specweb in FS mode. However,
if
I'm not sure exactly what you mean by 'available' - you can generate your
own checkpoints, certainly...But we don't provide checkpoints for any
benchmarks, just the facility for generating them.
Lisa
On Wed, Jul 8, 2009 at 11:16 AM, Sujay Phadke spha...@eecs.umich.eduwrote:
Hello,
I am not
/tutorials/asplos_pres.pdf. Just plop the m5
instruction where you want it in your rcS file and it will do it.
Lisa
On Mon, Jul 20, 2009 at 2:02 PM, Sujay Phadke spha...@eecs.umich.eduwrote:
Do you have the scripts to generate this?
- Original Message -
*From:* Lisa Hsu h
By default, a tick is a picosecond. How many ticks constitute a CPU cycle
depends on how fast you have your CPU running, i.e. if you have your CPU at
1GHz, then a CPU cycle is 1000 ticks.
Lisa
On Tue, Jul 7, 2009 at 2:04 PM, Devraj Chapagain drchapag...@gmail.comwrote:
HI,When tracing
Nate used to have some infrastructure to try this years ago. He'll have to
tell you the details, but I don't think it's been done since. And I'm not
sure he was ultimately successful - I think it had to do with the severe
mismatch of speedsM5 is way slower than an actual machine, obviously,
That's great that that will work! Remember though, if you want to
distinguish stats of software threads, you'll have to do additional hacking
because stats (like IPC, cache stats, etc) are with respect to hardware
contexts only.
Good luck!
Lisa
On Tue, Jun 9, 2009 at 8:14 AM, Veydan Wu
I don't think there's a way for you to know SOFTWARE thread ID, but you can
know hardware thread id with context_id. But if, for example, you context
switch out a software thread that runs on hardware context X, then the
hardware statistics for context X will be a combination of all the software
If you must do FS, then you can run a multi-threaded program on a CMP rather
than an SMT platform. You can use the set_affinity syscall to attach a
particular thread to a particular core. Search the archives, I'm sure it
has been discussed before on the mailing list.
Lisa
On Wed, May 27, 2009
Sorry for the big delay in replying to this, I was just cleaning out my
inbox and noticed this question.
What you want is a context_id. Theoretically, in an SMT system there are
context_ids, which are unique across the system, and cpu_ids, which are
unique to each core, and thread_ids, which are
As far as I know no one has ever run a JVM on M5, someone correct me if I'm
wrong.
I looked into it a while ago - since we really only have ALPHA as the
totally mature FS, you'd need a JVM for Alpha, which there used to be one
that was under development but seeing as I can't find it on the web
The kernel does not reside on the disk image so you don't have to make a new
image. You will have to compile your own vmlinux and point your sims to use
that binary.
Lisa
On Thu, May 28, 2009 at 3:05 PM, Shoaib Akram sakr...@illinois.edu wrote:
Thanks Rick. I am using the precompiled system
Here's the relevant wiki page
http://m5sim.org/wiki/index.php/Compiling_a_Linux_Kernel
On Thu, May 28, 2009 at 3:25 PM, Lisa Hsu h...@eecs.umich.edu wrote:
The kernel does not reside on the disk image so you don't have to make a
new image. You will have to compile your own vmlinux and point
www.m5sim.org should give you all the details you need for running
multiprogrammed workloads.
Lisa
On Tue, May 26, 2009 at 5:28 PM, Siddharth Gupta sidgu...@stanford.eduwrote:
Hi Steve,
Thanks for your reply. Could you give us some pointers on how this can be
done. Or point us to the right
Heh. Me neither, obviously. Sorry about that.
However, the mailing list archive is definitely helpful, there are a lot of
posts on this, some with sample bits of config script code.
Lisa
On Tue, May 26, 2009 at 5:38 PM, Steve Reinhardt ste...@gmail.com wrote:
Sorry, I didn't realize the
what are you doing with the simpoint? fast forwarding to it? a command
line might be helpful.
On Thu, May 14, 2009 at 2:42 AM, Pavan Kumar jorri...@gmail.com wrote:
hi steve.
i think there is effect because, every time i run simulation i check the
config.ini file. In config.ini under
You've got some funniness going on with your command line - why are you
using -s? That's normally only used if you're coming out of a checkpoint,
which you are not.
What do you want to do exactly, in terms of CPU models? Do you want to use
a checkpoint, or do you just want to run from the
The basic problem is that your version of M5 is too old to handle a binary
from a compiler that is too new.
What you'll need to do is update your version of M5 to the
development version, as the fix for this is only in that repository and has
not made it to stable yet.
If you do not want to do
how physical addresses are
assigned, you need to look at that page table structure and the places
it's used.
Gabe
Quoting Lisa Hsu h...@eecs.umich.edu:
Hi Meng-Ju,
Unfortunately I don't think there is an easy way to do this in SE. The
physical mapping is done in a pretty fake way, where
of execution, he'd still have to be able to
translate from the physical page numbers he assigned to the mmaped values so
that he can perform reads from memory.
Lisa
On Wed, Apr 8, 2009 at 5:40 PM, Lisa Hsu h...@eecs.umich.edu wrote:
Right, the page table *keeps track* of the mapping
Are you running with m5.opt or debug? If you run m5.fast and something goes
wrong, no errors will be printed since they've been compiled out.
Lisa
2009/3/19 Veydan Wu veyda...@gmail.com
Hi, Rick, Thanks for your reply.
The output of booting M5 seems normal, but the problem is it just quit
The closest thing we have to what you're looking for is the Timing CPU
model, which models a 1CPI in-order CPU, very basic, but models latencies
from the memory system.
Any stats you changed/added within the O3 CPU would not be transferred by
using the Timing model, but any stats from outside of
Note though, that maxtick is in terms of ticks, and not instructions.
I believe max-tick only works post-checkpoint or fastforwarding, but it's
easy to extend. Just grep for how options.max_inst is used in Simulation.py
and extrapolate - you can easily add it to stop on a non-ff or
Yes, it's point to point ethernet links. I'm not sure what you mean by
opposite, that's how I described it previously. You can make an arbitrary
network of point to point ethernet links.
Lisa
On Sun, Feb 22, 2009 at 10:17 PM, Aaron Williams aswi...@gmail.com wrote:
Lisa Hsu hsul
an mremap implementation has been push to the development tree, but i've
never tested it on sparc. in theory, it should work, but let me know if it
works for you.
lisa
On Fri, Feb 13, 2009 at 10:22 PM, Pavan Kumar jorri...@gmail.com wrote:
hi,
I am trying to run SPEC CPU 2006
I sent that last email, not Steve. And you should pull from the latest
tree, because I just pushed something. Undo your implementation and see if
the push works, and let me know how it goes.
Lisa
On Mon, Feb 16, 2009 at 6:22 PM, Pavan Kumar jorri...@gmail.com wrote:
Hi Steve,
Yes, it
Hi Xi,
Yes, that is something that happens in M5 due to the coherence protocol
(which is on no matter what kind of config you are running) and how we count
misses/accesses. I ran into this earlier.
Basically, some of the misses in the L1 are coherence misses but still
placed in the demand miss
I'm not sure what's up with the MAKEDEV script, it obviously used to work
but it has been a long time. Actually, now that I think about it, it
probably has to do with your platform, I bet the MAKEDEV shipped with
ptx-dist doesn't work with your platform, and if you typed which MAKEDEV
on your
The simpoint value *is* the number of instructions fast forwarded - you can
see all the values in cpu2000.py.
Lisa
On Sat, Jan 24, 2009 at 6:28 PM, Ashutosh Jain ashuja...@gmail.com wrote:
Hi there,
I am using fast forwarding technique using simpoint defined in cpu2000.py
file. I want to
Isuru,
I think probably your only bet is to go with FS mode. Like you found, there
is no thread scheduler in SE mode for M5, so running a non-SPLASH
multi-threaded workload would be more trouble than it's worth.
In FS mode, since you'd be running actual Linux, you'd have access to a real
thread
is the L2 cache but is this right?. Thanks so much for your
help.
On Fri, Dec 19, 2008 at 2:31 PM, Lisa Hsu h...@eecs.umich.edu wrote:
Hi Ryan,
The CPU is indeed connected to several ports, like for example the icache
port and a dcache port.
if you turn on the trace flag Config you
to be?. Thanks and sorry for the problems.
2008/12/19 Lisa Hsu h...@eecs.umich.edu:
yes, the problem is solved. the patch i sent out - instead of changing
it
to a higher number, change the line
testsys.cpu[i].max_insts_any_thread = 1
to:
testsys.cpu[0].max_insts_any_thread = 1
fix.patch and this is the output:
Hunk #1 succeeded at 122 (offset -9 lines).
Thank you.
2008/12/15 Lisa Hsu h...@eecs.umich.edu:
Try the attached patch.
To anyone interested:
for the initial switch from atomic to timing is set at
cpu[i].max_insts_any_thread = 1, for all cpu=i
the cpus? Would it
work just to schedule the event on cpu 0?
Steve
On Mon, Dec 15, 2008 at 2:39 PM, Lisa Hsu h...@eecs.umich.edu wrote:
Try the attached patch.
To anyone interested:
for the initial switch from atomic to timing is set at
cpu[i].max_insts_any_thread = 1, for all cpu=i
is that CPU 0 might
not be active at the moment and thus you would never hit the event
(e.g. if you switched out cpu 0 for something else).
Ali
On Dec 16, 2008, at 12:22 PM, Lisa Hsu wrote:
Yes, that would work too. Probably a better solution for this
case. It feels not as pretty
On Dec 16, 2008, at 2:52 PM, Lisa Hsu wrote:
The patch I sent does nothing but change the number of cycles the
initial atomic CPUs run before switching to timing in the standard-
switch scenario.
Steve's suggestion is just that only atomicCPU0 has a limit set, all
the rest run
I'm working on this. Stay tuned.
Lisa
On Fri, Dec 12, 2008 at 7:50 PM, Eduardo Olmedo Sanchez
eolms...@gmail.comwrote:
These are the changes that I did to the fs.py file:
np = options.num_cpus = 4
test_sys.l2 = L2Cache(size = '4MB', assoc = 4, latency = '30ns')
the probability that this will never happen again, but
doesn't rigorously remove that possibility. if anyone has a better idea of
how to fix this let me know.
Lisa
On Mon, Dec 15, 2008 at 9:44 AM, Lisa Hsu h...@eecs.umich.edu wrote:
I'm working on this. Stay tuned.
Lisa
On Fri, Dec 12, 2008
FYI, also, neither do writebacks.
Lisa
On Wed, Dec 10, 2008 at 5:12 AM, Ali Saidi [EMAIL PROTECTED] wrote:
An additional point is that read/write requests originating from a I/O
device don't have a CPU id/PC.
Ali
On Dec 10, 2008, at 8:19 AM, Joe Gross wrote:
Aah, I should clarify my
Since we don't provide a cpu2006.py file, you'll have to tell us what yours
looks like before we can diagnose the problem.
On Tue, Dec 9, 2008 at 9:38 AM, Pavan Kumar [EMAIL PROTECTED] wrote:
hi,
when i tried to compile the alpha binaries on M5 it gave the following
error message.
If you look in mem/cache/cache_impl.hh, you'll see
recvTiming/Atomic/Function implementations. So, when a bus sends a
sendTiming to the cache, the cache port on the other end of the bus port
does a recvTiming and does the appropriate things.
Lisa
On Tue, Dec 9, 2008 at 4:18 PM, Ryan Markley
Has anyone been able to run 450.soplex (either reference input) to
completion (or at least quite far) in SE or FS mode for Alpha?
Thanks,
Lisa
___
m5-users mailing list
m5-users@m5sim.org
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If you look at the Request object, there are accessor functions for the PC
and context id.
The Packet holds the MemCmd, which should help too.
Lisa
On Wed, Dec 10, 2008 at 12:43 AM, Joe Gross [EMAIL PROTECTED] wrote:
Hello,
Is it possible to somehow determine the program counter, thread ID
What happens with you turn on the trace flags? It could be a lot of things,
just asking what could it be? won't get any answers...if you could paste
the relevant output from the Exectrace that would help.
Also, I thik you mentioned before that it was your native machine running
2.6.9 and your m5
: Event_137: testsys.cpu progress event, instructions
committed: 0, IPC: 0
As you can see I get sometimes that the instructions commited are 0,
so I guess that something is going wrong, any ideas?, thank you.
On Wed, Nov 19, 2008 at 1:44 PM, Lisa Hsu [EMAIL PROTECTED] wrote:
Basically, yes
Try this:
http://m5sim.org/wiki/index.php/Frequently_Asked_Questions#OS.2FLinux_Related
That should help you add files to an image - you can just start with the one
we distribute.
Lisa
On Wed, Nov 19, 2008 at 4:05 PM, Eduardo Olmedo Sanchez
[EMAIL PROTECTED]wrote:
Hi I have been able to run
and has no accessor method).
Ali
On Nov 5, 2008, at 4:00 PM, Lisa Hsu wrote:
the very latest and greatest m5 has been changed to contextId() as
opposed to getCpuNum(). and there's a check now.
lisa
On Wed, Nov 5, 2008 at 3:55 PM, Ali Saidi [EMAIL PROTECTED] wrote:
pkt-req
That just means that you want the toolchain to reflect the same headers as
the kernel you want to build for M5. So, if for M5 you want to use kernel
2.6.22, then you should build your toolchain with those headers so they
won't be incompatible when you actually build the kernel, so no need to go
there has been interest, but as far as we know no one has made anything
publicly available or worked it to completion.
lisa
On Sat, May 24, 2008 at 10:09 PM, jerry lrui [EMAIL PROTECTED] wrote:
Hi,
I would like to analyze the power consumption using the M5 simulator. From
the mailing list I
are you using the cross compiler to compile your programs (as ali showed in
the previous email)?
lisa
2008/5/10 fractal218 [EMAIL PROTECTED]:
I downloaded the newest version of m5. It is Ok. Thank you!
--
送！送！送！正版瑞星2008半年免费！
mount it this way:
http://m5.eecs.umich.edu/wiki/index.php/Frequently_Asked_Questions#How_do_I_add_files_to_a_disk_image.3F
lisa
On Thu, May 8, 2008 at 6:16 PM, Mike Anderson [EMAIL PROTECTED] wrote:
Thanks,
But, I still can not see the img files.
I set up loopdevice
[EMAIL PROTECTED]
On Thu, May 8, 2008 at 8:04 PM, Gabe Black [EMAIL PROTECTED] wrote:
It looks like when you ran mke2fs you reformatted the image...
agreed. your image is fubar'ed so i'd download a fresh one and then follow
those instructions from the FAQ exactly. like nate said, this is somethign
we've all
doing this will result in millions of large files full of stat text - what
is it that you want this for?
lisa
On Sat, May 3, 2008 at 11:39 PM, jerry lrui [EMAIL PROTECTED] wrote:
Hi,
I want to dump m5stats after per cycle. I've looked up the code. Maybe I
can add some codes in function
didn't get the result I wanted. Could you
tell me
what is the correct way to get thest stats? Thank you very much!
Jerry
On 5/5/08, Lisa Hsu [EMAIL PROTECTED] wrote:
doing this will result in millions of large files full of stat text
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