Hi Vanchinathan,
At the moment, there is not a patch for m5op support for RISC-V. If you
want binaries to have access to performance counts, the best way to do that
would probably be to add CSRs for them and have those CSRs return the
values of the corresponding stats when read, like INSTRET,
Dear Alec
Thanks a lot for your prompt reply. I looked at the CSR counters and it
looks to me that I cannot find number of integer, load, store instructions
executed separately.
Ideally, if I can reset and dump stats using m5_dumpstats and
m5_resetstats, I can get detailed information on
Thanks Mohammad,
I really appreciate all the help; I’ll work on dist-gem5 now, test some more,
new kernel, new images, new DTBs in dist mode, new scripts and make some
measures.
If I hit another wall, I’ll ping again, also, if I can help in anything let me
know. In addition to that, if you
Hi gjins,
To the best of my knowledge, your reasoning is correct. If a packet goes
from cpu to the memory, it passes the local caches and then the shared
caches on its way to memory. Local caches from other cpu's are not passed,
thus meaning they are not on the path to memory.
It could be
Hi Gjins,
In your example, for any of the two cores, the path to the memory
includes its private caches and the shared cache and it does not include
the private caches of other core.
gem5's classic memory model implements a MOESI-like snooping protocol
and the cache that has the block with the
Hello,
I do understand that for multithreading in gem5 SE x86, I need to use
m5threads. Correct me if I am wrong.
Are m5threads supported on a 32 bit system ?
I found an old mail archive which says that it does not support.
Regards
Nidhi
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