I think running workloads fairly is very important in multi-core
experiments, because the number of executed instructions of each core can
be changed depend on each experimental configuration.
There is a prior work how to experiment fairly on multi-core system; A.
Hilton et al.,
It wold be great if you could review Gabe's patch on gerrit. Since it works
for you, giving it a +1 or a +2 would be appropriate.
On Wed, May 23, 2018 at 5:56 PM Tariq Azmy wrote:
> Thanks Gabe. Yeah it does not impact the program but it's just
Why don't you ask your university / supervisor for some more
resources? I think that is your best bet.
On Mon, May 21, 2018 at 6:57 PM, commerce _com wrote:
> Hi Ciro;
> I am a doctoral student in first year computer science, I work on armv8
> architecture on the
Hi commerce, I'm maintaining a fork of parsec at:
I don't have all benchmarks working, but I documented how everything
fails, and if you get something working, please send a pull request
there as well.
On Wed, May 23, 2018 at 12:51 PM, commerce
I am using FS mode.
On Thu, May 24, 2018 at 12:00 PM, Jason Lowe-Power
> Hi Da,
> Are you using SE mode or FS mode? IIRC, the TLB size does nothing in SE
> mode (it doesn't use a TLB). The TLB is only used in FS mode.
> On Thu, May 24, 2018 at 8:45 AM
The dtb read miss rate stays at 10%. Our workload is a simple sequential
linked list search microbenchmark with fixed heap size at 1MB. Cache size
is varied from 128KB to 2MB.
On Thu, May 24, 2018 at 11:44 AM, Da Zhang wrote:
> Hey guys,
> I tried to increase the
I tried to increase the dtb size (i.e., number of tlb entries) for our
research. However, the stats.txt for the different dtb size
(64,128,256,512,1024,2048,1048576) is practical identical or identical. For
size < 512, the system.switch_cpus.dtb.rdAccesses difference is only
Are you using SE mode or FS mode? IIRC, the TLB size does nothing in SE
mode (it doesn't use a TLB). The TLB is only used in FS mode.
On Thu, May 24, 2018 at 8:45 AM Da Zhang wrote:
> Hey guys,
> I tried to increase the dtb size (i.e., number of tlb entries) for
Hi Jason, Alec,
Thanks for the fast responses!
I can say I managed to run a lot of benchmarks on O3 and none of them
crashed. I did notice however that their performance on for distinct-width
O3 processors had only minor differences (on x86, the differences were much
Dear Haeyoon Cho.,
I am really thankful to you for this help. Actually, i am not very good in
modifying gem5 and this code will be very helpful for me.
I have one more question, is it good idea to normalize the stats with
number of instructions simulated to calculate energy or other things? Does
I'm not sure if RISC-V has been tested with the out of order CPU at all!
I'm happy that at least it doesn't completely fail!
For you problem of only fetching 1 instruction per cycle... I think it's
going to take some digging. My first guess would be that it could be a
Yes, gem5 does support the C extension (64-bit version only, though). I
don't know what could be causing your particular issue. I'm not sure
advancePC is the issue, though, because all that essentially does is call
PCState::advance(), which is inherited unchanged from
I recently switched from gem5/x86 to gem5/RISCV due to some advantages of
I'm getting some weird simulation results and I realized my compiler was
generating instructions for the compressed RISCV ISA extension (chp 12 in
the user level ISA specification
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