[gem5-users] Re: Segmentation Fault when trying to execute mrs x0, mpidr_el1

Hi Siva, An SE simulation implicitly runs at EL0, and reading MPIDR_EL1 is undefined at EL0 (unless FEAT_IDST is implemented, which is not currently the case in gem5). It looks like gem5 is segfaulting instead of failing more gracefully in this case, but in general you won’t be able to read

[gem5-users] Resetting and dumping stats in Gem5

Hi All, I want to reset the gem5 stats before the start of ROI (region of interest) and dump the stats as soon as the ROI completes. I looked into a few old mail archives, but was unable to locate m5op.h header for resetting and dumping the stats. Could anyone guide me through the correct way to

[gem5-users] What happens when a atomic only port is accessed in Timing simulation?

Hi All, I am building a simulated system with a control registers port that only implemented recvAtomic function. The control port is connected to the IOBridge, and the system is running in timing mode. There is no problem to access the registers from CPU, but I wonder what the