Re: [gem5-users] SSE Instructions in Gem5

To directly answer your question: The labeling of instruction in gem5 is not accurate at all. Feel free to fix the labeling and submit a patch to reviews.gem5.org, though! We'd welcome the fixes. BTW, you're correct that SIMD instructions are labeled as floating point instructions. I've noticed

Re: [gem5-users] Gem5-Ruby component-Cache coherence protocol simulation

Hello, I think there may be a couple of mistakes in your command line: "./build/ARM/gem5.opt configs/example/se.py --ruby --cpu-type timing -c testa/test-progs/hello/bin/X86/linux/hello" First, it looks like you've build gem5 with support for the ARM ISA, but you're trying to run an X86 binary.

Re: [gem5-users] [gem5-dev] Creating new SimObject error

Hi Mohamed, The gem5-users list is probably a better place to ask this question (forwarding it there). It's not totally clear from your email what "CLASSONE" is, though I appreciate all of the detail :). However, the error that you're seeing is because you didn't set the variable named

Re: [gem5-users] Gem5-Ruby component

That error is saying the file " tests/test-progs/hello/bin/X86/linux/hello" doesn't exist. I think you need a lowercase X86 (x86). Jason On Thu, Jun 23, 2016 at 6:04 AM <206115...@nitt.edu> wrote: > > Hi > > > ./build/X86/gem5.opt configs/example/se.py --ruby --cpu-type=timing -c >

Re: [gem5-users] scp between gem5 simulated linux system and real linux system

Hi Liyang, You're correct that you can't use scp because gem5 doesn't have an ethernet connection to the outside world. What we usually do to get data onto the disk images is mount the disk image on the host machine and make modifications, then boot the disk image with gem5. You can use the

Re: [gem5-users] Making a C application work on multiple cores with gem5

Hello, If you're using full system mode (FS mode), you can use pthreads or any other threading library just like on a real machine. If you're using syscall emulation (SE) mode, then you can use the m5threads library which is a pthreads-like library (http://repo.gem5.org/m5threads/). If I've

Re: [gem5-users] Physmem in SE Mode

Hi Monir, The AbstractMemory class (along with the System class) implements the physical memory of the system. When configuring gem5, if you instantiate a memory object (e.g., DRAMCtrl like DDR3_1600_x64) this object will register the physical memory with the System object. The with the DRAMCtrl,

Re: [gem5-users] Adding a new GPU model

Hi Sebastian, You can also check out gem5-gpu https://gem5-gpu.cs.wisc.edu/wiki/ as another example of how to integrate a GPU model into gem5. Feel free to send us questions on gem5-gpu-dev@googlegroups. Cheers, Jason On Tue, Aug 9, 2016 at 2:31 AM Andreas Hansson

Re: [gem5-users] Physmem in SE Mode

Hi Monir, It still seems like the MinorCPU just isn't compiled in. I don't have time right now to try it myself to see how to do it. Another thing you can do to check to see if the MinorCPU is compiled is to look at the generated files in build/.../cpu. These files are in the same directory

Re: [gem5-users] Physmem in SE Mode

Yes, I would try deleting the entire build (build/, not just build/SPARC) directory and recompiling from scratch. I'm not familiar with the details of the T1's coherence protocol. If you really care about modeling the coherence protocol, then you should be using the Ruby memory model. You can

Re: [gem5-users] Physmem in SE Mode (Jason Lowe-Power)

on work on multiple cores with gem5 > (anoir nechi) >2. Making a C application work on multiple cores with gem5 > (anoir nechi) > 3. Virtual to Physical Address in ARMv8 FS Classic Memory > (Vanchinathan Venkataramani) > 4. Re:

Re: [gem5-users] Physmem in SE Mode

@Andreas, I agree with what you said. I didn't word my previous email very carefully. I meant, that if you want to model the *specific coherence protocol* of the T1, then you probably want to use Ruby (and would likely need to write a new protocol). @Monir: Sounds like you got it working finally!

Re: [gem5-users] GEM5 SPARC SE mode O3 CPU - no TLB info

Hello Monir, You're correct that in SE mode the TLB is never accessed. You'll have to use FS mode if you want to use a TLB model. If you want to dump periodic stats, you can use a method similar to how the Simulation.py script takes periodic checkpoints. You can put "m5.simulate(period)" in a

Re: [gem5-users] Cache warmup with ruby

Hello, All you have to do is exit the simulation after 500 million instructions and then reset the stats. You can exit the simulation after a certain number of instructions easily (see what the -I option does). Then, you simply call m5.stats.reset() from Python to reset the stats. Then, you can

Re: [gem5-users] cache coherence protocol using ruby memory model

See http://qa.gem5.org/140/scons-2-0-10-and-swig-with-python-2-7-5-on-gem5. I believe this is a problem with your swig version. See also http://gem5.org/Dependencies. Cheers, Jason On Mon, Jun 27, 2016 at 4:41 AM <206115...@nitt.edu> wrote: > > Hi everyone, > > I want to simulate MESI cache

Re: [gem5-users] SSE Instructions in Gem5

te: > >> Thanks Jason. I'll try to fix it and possibly submit a patch. >> >> >> >> On Wed, Jun 22, 2016 at 9:30 AM, Jason Lowe-Power <ja...@lowepower.com> >> wrote: >> >>> To directly answer your question: The labeling of instruction in gem5

Re: [gem5-users] Operation Classes in Arm

Or even better, post the patch on reviewboard (http://reviews.gem5.org) so we can incorporate your work! Cheers, Jason On Sat, Jul 9, 2016, 8:08 PM Ayaz Akram wrote: > Hi Fernando, > > Will it be possible for you to post the relevant code here ? That will > just save some of

Re: [gem5-users] Physmem in SE Mode

Hi Monir, The protocol is only used if you are using the Ruby memory model (e.g., --ruby option). Otherwise, the memory system is the classic memory model. Classic uses something like "MOESI" coherence, but it's not modeled in as much detail as Ruby's coherence protocols. I'm not sure why you're

Re: [gem5-users] Enable Printing in Linux 4.3

Hello, These are not printed to stdout in full system mode, but are saved in the terminal file (something like system.pc.com_1.terminal). You can also see the terminal output if you telnet into the guest system (e.g., using m5term in gem5/util/term). Cheers, Jason On Thu, Jun 30, 2016 at 4:48

Re: [gem5-users] Restoring from the checkpoint created by hack_back_ckpt.rcS

Hi Azadeh, I'm not certain what the problem is. However, you don't have to use the O3 CPU to "restore-with". That option is the CPU that is used during checkpoint restore, not the CPU used once checkpoint restore is complete on the main simulation. To choose which CPU to use for the main

Re: [gem5-users] Enable Printing in Linux 4.3

e this helps. Jason On Thu, Jun 30, 2016 at 10:44 AM Vanchinathan Venkataramani < dcsv...@gmail.com> wrote: > Hi Jason > > I cannot see the output in system.terminal file. I am using the latest > gem5 version. > > Best regards > V Vanchinathan > > On Thu, Jun 30, 20

Re: [gem5-users] real run-time of the benchmark

sim_seconds is the time in the simulated system. host_seconds is the time on the host. You want to use sim_seconds for the performance of simulated applications. Jason On Mon, Aug 15, 2016, 8:03 AM leila zamani wrote: > There are "sim_seconds" & "host_seconds" in the

Re: [gem5-users] Use m5ops "m5_dumpreset_stats()" In SE mode

Hi Anouar, It looks like you're getting a linking error. Make sure that you either include the appropriate assembler (.S) file in your compiling step, or assemble the .S file and link the appropriate object (.o) file. Cheers, Jason On Sun, Aug 14, 2016 at 11:36 AM anoir nechi

Re: [gem5-users] ARM big.LITTLE

Hi Felipe, I'm not super familiar with the ARM model (and these weird dtb files), but I believe the rcS file that the simulator is looking for is actually on the host. This somewhat describes how FS simualation works: http://gem5.org/Running_gem5#Basic_Operation. The rcS file is a script which is

Re: [gem5-users] Physmem in SE Mode

Hi Monir, I really don't know much about the internal workings of the MinorCPU model (or really any of them). If you can track the problem down to something specific, and still can't figure out the solution, I'd suggest posting a new thread here on the users list. Cheers, Jason On Fri, Aug 12,

Re: [gem5-users] FW: Gem5-Ruby_HBM_Parsec_Deadlock

Hi George, I was only saying that your system with 8 HBM controllers is much more bandwidth than the original developers of Ruby imagined. Therefore, I wouldn't be surprised if you are encountering some bugs that others have never seen. MESI_two_level is one of the more tested protocols, so I

Re: [gem5-users] The latest version of x86 Linux kernel

Hi Jasmin, 12.04 is pretty ancient too, it's over 4 years old now! Either way, from what I hear, it's pretty easy to compile your own kernel and get it to run on gem5, for both x86 and for ARM. However, I don't have any direct experience. I expect you would probably need to modify the config

Re: [gem5-users] creating multiple socket system

Hi Wei, If you're using Ruby, you probably just need to configure the network topology to match a dual-socket system. In fact, most of the topologies were originally written with multi-socket systems in mind. Check out configs/topologies/*. You may also need to modify the coherence protocol

Re: [gem5-users] How to artificially delay one of the programs in multi-program workloads?

Hi Reza, I've never tried to do this, and I'm not sure if it's fully supported or not. However, this is what I would try. Note, all of this can be done from the Python config file, I believe. 1. Create the process/workload/cpu threads in the normal way. 2. "switch out" the CPU or somehow disable

Re: [gem5-users] error to increase mem-size

This looks like you ran out of memory on the host platform. There is an option for the System object to use an mmap flag that does not pre-allocate memory, but you still may run into issues. gem5 does not support simulating more guest memory than what is available on the host machine (i.e., gem5

Re: [gem5-users] gem5 energy output

Hi Ayman, gem5 has some support for energy modeling for a few objects (e.g., the DRAM controller, maybe others). However, it does not have energy numbers for the CPU cores. To get CPU-core energy you would need to take the gem5 stats output, which includes functional unit activation information,

Re: [gem5-users] uncacheable addresses

property. > Any thought on this? How can I set the uncacheable flag? > > Thanks, > Lorenzo > > > 2017-01-27 17:04 GMT+01:00 Jason Lowe-Power <ja...@lowepower.com>: > > Hi Lorenzo, > > If the access flows through the cache, the cache might be creating an MSHR >

Re: [gem5-users] Inconsistent big integer multiplication results comparing physical machine with full-system simulation mode

Hi Shuai, A couple of things you could try: 1) Running in SE mode instead of full system. Is there something in the simple test case that requires full system? 2) I quickly tried running the code in SE mode myself, but it looks like it's using some pthreads functions. Can you provide the minimal

Re: [gem5-users] Unsupported operation at m5_exit()

-e -r configs/example/fs.py --script > util/rcS/foo.rcS > > > > And this one for restarting from the checkpoint: > > > >> ./build/ARM/gem5.fast -d chkpt-dir/timing -e -r configs/example/fs.py > --script util/rcS/foo.rcS --cpu-type timing --caches --checkpoint-dir >

Re: [gem5-users] Source and Destination Registers in StaticInst

Hi Wil, I'm not sure exactly what you're trying to do, but you could probably look into the CPU model code to see how they do dependency checking. It may also be possible to use the CPU probe interface to probe into the CPU models to see the dependency chains. Jason On Mon, Feb 6, 2017 at 12:26

Re: [gem5-users] Requests to Main Memory

Hi Reza, This is handled by the port interface between the cache and the main memory. For instance, at the DRAM controller, every request calls recvTimingReq(). You may learn something from this chapter of my book: http://learning.gem5.org/book/part2/memoryobject.html. The caches and the memory

Re: [gem5-users] Unsupported operation at m5_exit()

Hi, What is the command you're using to build the executable? I'm unable to reproduce this bug with the following command: gcc -o hello hello.c util/m5/m5op_x86.o I also tested for ARM. It shouldn't be possible to compile without a parameter to m5_exit. Also, looking through the code, as long

Re: [gem5-users] ARM RUBY/Garnet NOC full system error

mber 1299panic: Not all stats have been initialized.You > may need to add ::regStats() to a new SimObject's regStats() > function. @ tick 0* > [baseCheck:build/ARM/base/statistics.cc, line 226] > Memory Usage: 1771200 KBytes > Program aborted at tick 0 > --- BEGIN LIBC BACKTRACE

Re: [gem5-users] help

Hello, This is probably a bug in the network test config file. This is not a script that is run very often, so I wouldn't be surprised at all if there was something wrong. The error you're seeing is occurring somewhere in the Python configuration files. I think it's happening before gem5's

Re: [gem5-users] L1 Cache Port Width Size

Hi Yasir, gem5's ports are not as much of a physical model as they are a programming API. The "width" of the CPU->cache connection is determined by the CPU model (how many requests the CPU can issue per cycle) and the cache model (how many requests the cache can accept per cycle). The CPU (or any

Re: [gem5-users] Implementing Cache Hierarchy for running ASIM/MOBY benchmark

Hi, It's unfortunately not that simple to extend the fs.py script. It uses complex and inflexible logic to set up the system. I would strongly encourage you to write your own script from scratch to support this. You can find an example for X86 here: http://learning.gem5.org/book/part3/index.html.

Re: [gem5-users] Number of instructions Vs number of ticks + resetstats + checkpointing

Hi Ali, Since you're doing something that isn't fully supported by the fs.py script, I would suggest making your own config file. The fs.py script, and the other supporting scripts in common/, are not very flexible, and when you want to do something that is a little outside of the norm it becomes

Re: [gem5-users] Issue with creation of L3 Cache (and tol3bus)

This is hard to understand what's going on, but I'll try: The error is "AttributeError: object 'O3_ARM_v7a_3' has no attribute 'tol3bus'". This means that you are referencing the variable tol3bus before it is defined. Did you add this variable to the ARM CPU? It would probably make more sense for

Re: [gem5-users] Compiling binary for x86_64 for Syscall Emulation

the binary and I'll try it out on my gem5. Have you tried any other binaries and seen a similar error? Cheers, Jason On Fri, Jan 20, 2017 at 11:10 AM <maitysancha...@gmail.com> wrote: > Hello Jason, > > On 17-01-20 15:33:23, Jason Lowe-Power wrote: > > Hi Sanchayan, >

Re: [gem5-users] Assign an specific memory address range to each program (core)

Hi Reza, You can find the physical memory allocation code for SE mode in src/sim/system.cc (System::allocPhysPages) and src/sim/process.cc (Process::allocateMem). This should get you started with what you're trying to do. You can also modify the page table for each process from the Python config

Re: [gem5-users] Compiling binary for x86_64 for Syscall Emulation

port working better that you can test, too ;). http://reviews.gem5.org/r/3793/ Cheers, Jason On Mon, Jan 23, 2017 at 9:34 AM Jason Lowe-Power <ja...@lowepower.com> wrote: > Hi Sanchayan, > > gem5 does have support for dynamic executables on Linux x86 platforms. I'm > not certa

Re: [gem5-users] Cleaning the gem5 build directory

Hi Somnath, I usually just delete the entire build directory. However, you should rarely need to do a full rebuild. The only changes that require it are changes to the "global" scons variables. Jason On Wed, Jan 25, 2017 at 4:51 AM Mukherjee, Somnath wrote: > All, > > I am new

Re: [gem5-users] uncacheable addresses

hould not be treated as a normal cache miss > (cache-line-refill). > > Any thought on how to fix that? > > Thanks, > Lorenzo > > > 2017-01-26 18:06 GMT+01:00 Jason Lowe-Power <ja...@lowepower.com>: > > Hi Lorenzo, > > This error means you're trying to ac

Re: [gem5-users] Warm up improvement

Hi Ferran, I don't recall any patches posted to reviewboard to implement this functionality. However, you can check yourself on our reviewboard server: http://reviews.gem5.org/. Additionally, you may want to email the authors directly and ask if they have a public repository for the code.

Re: [gem5-users] Deadlock using m5threads

Hi Alberto, m5threads is not a perfect implementation of pthreads. Since m5threads doesn't use the futex system call, there are a number of cases where it won't behave the same way as pthreads. I've specifically run into a problem using pthread barrier where I had to re-write my code to use sense

Re: [gem5-users] Creating Tiled chip architecture in gem5

Hi Bhaskar, If you are concerned with modeling interconnection networks you should use Garnet, not the SimpleNetwork. Note: Both of these are part of Ruby, so you have to use the Ruby caches, not the classic caches. Additionally, to create at tiled architecture in Ruby will involve writing your

Re: [gem5-users] Regarding malloc implementation in gem5 SE mode

Hi Navin, I would look at Process::allocateMem in src/sim/process.cc and brkFunc() in src/sim/syscall_emul.cc. brkFunc is called every time the process exectute the sbrk system call which increases the size of the heap. You could probably modify Process::allocateMem to specify which virtual

Re: [gem5-users] Running ASIM on Gem5 + Android

Hi Sneha, The error is "system.membus.forward_latency without default or user set value". You can solve this in two ways. 1) somewhere in your config file set the forward_latency for the membus (e.g., system.membus.forward_latency = 12 or whatever latency you think is appropriate). Or 2) If you

Re: [gem5-users] Simulate Dual-Core in gem5

Hi Qingran, gem5 models the entire system including caches and the memory hierarchy. Most communication between cores occurs through the memory hierarchy. So you can simply modify the program to communicate via shared memory. If you want to implement some new communication hardware between CPUs,

Re: [gem5-users] Running gem5 simulation faster on multiple host CPU?

Hi Somnath, gem5 is a single-threaded simulator, for the most part. There is some support for assigning event queues to multiple threads, but it isn't fully fleshed out except in very limited circumstances (e.g., two systems connected via ethernet). However, there are a number of different ways

Re: [gem5-users] Deadlock using m5threads

. > > Could you provide me some documentation about how to use dynamic link in > SE with X86? > > Thank you very much. > > Regards, > > Alberto. > > > El 2017-02-21 16:17, Jason Lowe-Power escribió: > > Hi Alberto, > > > > m5threads is not

Re: [gem5-users] Different number of sim cycles among the CPU cores

Hi Ali, First, I would check to be sure you're simulating what you expect. Is there a way for you to print out what the simulated system is doing (say, by logging in with m5term and running top)? This would at least eliminate one potential source of the problem. Second, it's possible that the

Re: [gem5-users] gem5 Checkpoints for different ISAs

hould have been done by both binaries if the input is > same in both cases. That does not seem to be the case ! > > On Mon, Feb 13, 2017 at 12:05 PM, Jason Lowe-Power <ja...@lowepower.com> > wrote: > > Hi, > > Another difference between ARM and x86 is the OS that you'r

Re: [gem5-users] Simulating a multi-ported XBar-cache connection

Hi Subhankar, You can increase the width of the crossbar. Though, I believe after 64B increasing the width does not make a difference. You could also increase the clock rate of the crossbar (e.g., 2X the cache clock) to simulate a multi-ported crossbar. Finally, you could add a new crossbar

Re: [gem5-users] Parsing options in hmctest.py

Hi Muzamil, I think you should try familiarizing yourself with Python option parsers. For instance https://docs.python.org/2/library/optparse.html. With this, you can specify and act on command line parameters. Then, it is up to you to use those command line options in your Python code to change

Re: [gem5-users] FS Simulation using HMC_2500_x32 and Caches

Hi Muzamil, Note that if you want to perform experiments with gem5 comparing the performance of different system configurations *you must use timing mode*. You cannot get timing numbers when using the atomic CPU or running with atomic memory mode. The error you are seeing is because of the

Re: [gem5-users] ARM RUBY/Garnet NOC full system error

' > failed. > Program aborted at tick 0 > Build commands are > > scons build/ARM/gem5.debug PROTOCOL=MI_example -j2 > ./build/ARM/gem5.debug --debug-flags=Exec,ExecTicks > configs/example/fs.py --machine-type=VExpress_GEM5_V1 --kernel > /home/khilji/gem5/m5/system/binaries/vmlinux-aa

Re: [gem5-users] gem5 Checkpoints for different ISAs

Hi, Another difference between ARM and x86 is the OS that you're using. Maybe the different paths are actually different paths through the OS (or interrupts, etc.) and not different paths through your binaries. Even in SE mode there may be different code paths based on how the syscalls are

Re: [gem5-users] Help needed creating and joining a new thread several hundred times (total n=2)

Hi Shail, It looks like gem5 isn't freeing the guest physical memory of the old threads in SE mode. I'm not surprised there's a bug here. I haven't heard of anyone testing this! You could take a look at the code for pthread_join both in m5threads and in gem5 (somewhere in sim/, probably). If you

Re: [gem5-users] ARM RUBY/Garnet NOC full system error

, > > You mean in system.terminal file in m5.out. There is nothing in it > ..blank. I have also tried with linux-aarch32-ael.img but the result is the > same. Any suggestions plz ? > > best regards, > sharjeel > > On 13 February 2017 at 22:02, Jason Lowe

Re: [gem5-users] ClockedObject Warning

Hi Ali, You can ignore this warning at the beginning of simulation. The warning is pretty self-explanatory. After adding some power modeling information to gem5, there is a warning if you change power states more than once at the same moment (which is physically impossible). But since this is at

Re: [gem5-users] Parsing options in hmctest.py

Hi Muzamil, You have to also change the Python code which sets this parameter on the DRAM controller. You can also use python print statements to make sure things look as they should. Finally, you can check the config.ini file to make sure these changes propagated. Jason On Wed, Feb 8, 2017 at

Re: [gem5-users] A tutorial of gem5+kvm for X86

Hi Ali, First, I don't think using the KVM CPU is going to help you too much in speeding up the simulation. The only thing you can do with the KVM CPU is to fast-forward. There is no timing simulation with KVM. KVM can be used in conjunction with sampling, or with multiprocess support to speed up

Re: [gem5-users] ARM RUBY/Garnet NOC full system error

Hello, Ruby is known to have issues when using the ARM ISA. It's likely a problem with how the system is configured. I would strongly encourage you to not use fs.py, but to write a new Python configuration script from scratch if you need to do unsupported things like ARM + Ruby. Another option is

Re: [gem5-users] Build failure with latest master branch

Hi Sanchayan, There's a change on RB that needs to be pushed ( http://reviews.gem5.org/r/3779/) that fixes the issue with protobuf. You can download this change and apply it with "hg qimport && hg qpush". For the Python issue you ran into, you can run the following find/sed command to "fix" it.

Re: [gem5-users] Compiling binary for x86_64 for Syscall Emulation

Hi Sanchayan, I'm not sure what the problem is when you're running hello. I believe you've compiled it correctly. The error indicates that the application is trying to read an address that was never allocated. To figure out the issue, I would follow these steps: 1. Make sure the binary executes

Re: [gem5-users] Manipulation data in Cache with Gem5

Best > > Emin.. > > 9 Ara 2016 Cum, 10:29 tarihinde, Jason Lowe-Power <ja...@lowepower.com> > şunu yazdı: > > Hi Emin, > > You can start by looking at the cache code in src/mem/cache. It should be > pretty obvious where the data is stored (e.g., see line 77 in c

Re: [gem5-users] Using m5_switchcpu in SE mode

Hi Tod, This is a good question, and it isn't documented anywhere very clearly. The main way to support switching CPUs, is to use the Python config files. At a high-level your config file should look something like this: m5.simulate() m5.simulate() First, you create your system as normal,

Re: [gem5-users] Running FS without linux

Hi Stefano, There is some support for FreeBSD in gem5, and I believe there is at least one person who has gotten it working recently. For other OSes and bare metal, for the most part, gem5 should work. However, there will almost certainly be some bugs and some small features you would have to

Re: [gem5-users] SE Mode Running Error

Hi, This question is appropriate for the gem5-users mailing list, not gem5-dev. I've removed the gem5-dev list, which is used for developers of gem5 to talk about code changes. The problem you are experiencing is spelled out via "warnings" and "fatals" in your screenshots: "fatal: Object file

Re: [gem5-users] HMC Simulation

Hi Muzamil, For the Learning gem5 two-level script, there was a bug in an old version of it. It should be "system.cpu.interrupts.pio[0]". The correct script can be downloaded here: http://learning.gem5.org/book/_downloads/two_level.py. (Note: the cannonical version of the book now lives at

Re: [gem5-users] Multithreading in gem5, full system mode

Hi Jasmin, gem5 is an event-driven simulator. So, when there are multiple objects (e.g., multiple CPU cores, or caches, or memory controllers, etc.) all of these objects can execute in parallel in simulated time (or guest time to use virtual machine nomenclature). The CPU models don't necessarily

Re: [gem5-users] Multithreading in gem5, full system mode

4 cores and 4 threads, within once cycle, > each of them executes tick() on their own? > > > > Best regards, > > Jasmin > > > > On Tue, Jan 17, 2017 at 3:59 PM, Jason Lowe-Power <ja...@lowepower.com> > wrote: > > Hi Jasmin, > > > > gem5 is an event-dr

Re: [gem5-users] gem5-users Digest, Vol 126, Issue 14

ts of gem5-users digest..." > > > Today's Topics: > >1. HMC Simulation (Muzamil Rafique) >2. Re: HMC Simulation (Andreas Hansson) >3. Multithreading in gem5, full system mode (Jasmin Jahic) >4. Re: HMC Simulation (Jason Lowe-Power) >5. Re: Multithreadi

Re: [gem5-users] Compiling binary for x86_64 for Syscall Emulation

of this file to find out what is causing the issue. Cheers, Jason On Thu, Jan 19, 2017 at 1:19 PM <maitysancha...@gmail.com> wrote: > Hello Jason, > > On 17-01-19 15:24:18, Jason Lowe-Power wrote: > > Hi Sanchayan, > > > > I'm not sure what the problem is whe

Re: [gem5-users] Ubuntu, booted on gem5, is not syncing the file-system?

Hi Somnath, By default the disk image is created as a "COW" or copy-on-write image. Thus, all changes made to the disk are made to an new copy that is deleted when gem5 exits. If you want your changes to be permanent you need to modify the way the disk image is created and use a raw disk image,

Re: [gem5-users] l3 cache

A more up-to-date version of the tutorial can be found at http://learning.gem5.org. This is where it will live for the foreseeable future. Jason On Mon, Feb 27, 2017 at 5:58 AM Serhat Gesoglu < serhat.geso...@manchester.ac.uk> wrote: > Hello, > L3 cache is not implemented in gem5 but you can

Re: [gem5-users] gem5 segmentation fault with SPEC CPU2006 benchmarks

Hi Muzamil, Have you tried running gdb to find where the segfault is occurring. That's where I would start. Using some debug flags would be helpful too after you narrow down the problem. Cheers, Jason On Wed, Feb 22, 2017 at 6:31 PM Muzamil Rafique wrote: > Hi

Re: [gem5-users] Linux booting problem in ARM NOC

on CPU 0 > hw-breakpoint: CPU 0 failed to disable vector catch > hw-breakpoint: Debug register access (0xee113e93) caused undefined > instruction on CPU 1 > hw-breakpoint: Debug register access (0xee013e90) caused undefined > instruction on CPU 1 > hw-breakpoint: Debug register access

[gem5-users] Announcing gem5's move to git

Hi all, It's been a while in the making, but we're moving all of the gem5 code from mercurial to git and our hosting onto Google's cloud (big thanks to Google for donating the resources, Andreas Sandberg for driving this, and the team at Google for helping us out). We will be migrating our

Re: [gem5-users] Ubuntu, booted on gem5, is not syncing the file-system?

e any of the files being written to the disk image! > > > > Is there anything else I am missing? > > > > Regards, > > Somnath > > > > *From:* gem5-users [mailto:gem5-users-boun...@gem5.org] *On Behalf Of *Jason > Lowe-Power > *Sent:* Monday, February 27,

Re: [gem5-users] Running full system with SMT

Hi Ferran, First, for SMT support, I believe it is implemented in the O3 CPU, and you should be able to enable it by updating your CPU configuration (numThreads, see src/cpu/BaseCPU.py). However, as far as I know, SMT is not tested in our regression tests, so it's possible (likely) that there are

Re: [gem5-users] SPARC_SE -> Unimplemented Instruction

Hi Monir, I won't belabor the point about using a better supported ISA this time :). For your other options, I definitely wouldn't change the instruction to a warning. That may be appropriate for a few instructions, like prefetch, but it's inappropriate for most. I don't know the SPARC ISA off

Re: [gem5-users] Minor Cpu x86

Hi Ayaz, This sounds like a bug to me. You should post your fix on reviewboard ( http://reviews.gem5.org/) so we can incorporate it into the mainline gem5. Thanks! Jason On Tue, Sep 6, 2016 at 2:00 PM Ayaz Akram wrote: > I'll appreciate if someone who has used x86 minor cpu

Re: [gem5-users] SPARC_SE -> Unimplemented Instruction

Hi Monir, No, I don't have any good suggestions for you. Too bad you're not inside ARM. I bet they have something internally ;) (note: I have no knowledge of what ARM may or may not be doing internally). Another (semi-)sarcastic response: It may be less effort to add the RISC-V ISA to gem5 than

Re: [gem5-users] Rebuilding after changing config files

Hi all, Just to be totally clear: Re-compiling gem5 is *only required if you modify something in src/*. No changes to any files in configs/ require compiling gem5 again. (Note: even if you modify .py files in src/ you have to recompile.) The only other time that a compile is required is if you

Re: [gem5-users] Stuck at "initiateAcc not defined!"

Hello, Try running the script that ships with current gem5 (not gem5-stable). You can find up-to-date learning gem5 scripts in configs/learning_gem5. Cheers, Jason On Wed, Aug 31, 2016 at 8:09 AM Oscar Rosell wrote: > Could you send the contents of simple.py file? >

Re: [gem5-users] RISC-V ISA

Hi Alex, This is very exciting. I think I was just telling somebody a day or two ago that RISC-V would be great to have in gem5! For the submission process see http://gem5.org/Submitting_Contributions. Also, you should be sure to follow the coding style: http://gem5.org/Coding_Style. In the

Re: [gem5-users] RISC-V ISA

ns to use this, please cite "RISC5: Implementing the > RISC-V ISA in GEM5," which we plan to submit soon. > > Thanks, > Alec Roelke > > On Fri, Sep 9, 2016 at 10:07 AM, Jason Lowe-Power <ja...@lowepower.com> > wrote: > >> Hi Alex, >> >> This is very ex

Re: [gem5-users] arm_detailed error

Hi Anouar, You're seeing this error because the script configs/common/CpuConfig.py isn't importing your script correctly, or something. See line 138 in the aforementioned file. I would bet there is an error in your file causing it to throw an exception when it is imported. You can remove the try

Re: [gem5-users] ARM config error

Hi Anouar, I'm not sure what's going wrong. I would run gem5.debug in a debugger and trace back where the stat is being defined that is causing the error. It's likely that you didn't instantiate some object that some other object expects. Note: the simple scripts in the Learning gem5 book were

Re: [gem5-users] Running ad hoc workload

Hi Jasmin, I'm not sure if I totally understand what you're trying to do, but I think I can give some pointers in the right direction. First, to "control gem5" you can use any python script that you create. There is a python API, and in fact, that's what all of the scripts in configs/examples

Re: [gem5-users] RISC-V ISA

Hi Monir, You should just download the patches off of reviewboard and test them. Having someone else use them will be a great way to increase the test coverage. If you have any issues while you're using them post the issues to reviewboard. For the timeline to get something accepted... it's hard

Re: [gem5-users] Custom memory mapping

Hi Seshan, I'm not sure if I totally follow what you're trying to do, but I'll do my best to give you some relevant information. In gem5, there is an AddrRange class. You can set each cache (or memory controller, or any slave port) to respond to some specific set of AddrRanges. Thus, if you

Re: [gem5-users] gem5-users Digest, Vol 123, Issue 2

Yes, please don't use gem5-stable. gem5-stable is just an arbitrarily old version of the gem5 development repository. We are currently discussing the best way forward for gem5-stable, and it looks like we're going to just remove it. Cheers, Jason On Thu, Oct 6, 2016 at 3:53 PM Monobrata Debnath

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