[gem5-users] gem5 has encountered a segmentation fault!

2017-07-17 Thread Neu, Markus
Hallo, on the try of sending a copy of the data packet to a new module the simulator is encountering a segmentation fault. I had extended the cache.cc with a additional port and the Cache::recvTimingReq(PacketPtr pkt) with the send statement: dapuSidePort->sendAtomic(pkt); for these port. On

Re: [gem5-users] undefined reference to `vtable for Port

2017-07-17 Thread Neu, Markus
:39 An: gem5 users mailing list Cc: m5-us...@m5sim.org Betreff: Re: [gem5-users] undefined reference to `vtable for Port Hi, This looks just like a C++ error. Check solution for: https://stackoverflow.com/questions/3065154/undefined-reference-to-vtable Regards, Oscar On 15 Jul 2017, at 17:47,

[gem5-users] undefined reference to `vtable for Port

2017-07-15 Thread Neu, Markus
Hallo, at the moment i try to add a additional port to the cache.cc/.hh. The idea is to send a copy of the packets to a new module. I use a example from: learning.gem5.org/book/part2/memoryobject.html as template for the port

[gem5-users] vector ports

2017-08-05 Thread Neu, Markus
Hallo, at the moment i try to create vector ports. I used: http://learning.gem5.org/book/part2/simplecache.html to get an idea how to do this, but the example is not working. The implemented port is still not a vector port. What i have is: declaration inside the header:

[gem5-users] adding a new module

2017-06-28 Thread Neu, Markus
Hallo gem5 team, i am a completely newbie with gem5. The aim is to construct a new module on top of the cache. So far i used the tutorial from "learning.gem5.org" to understand how a module has to look like. Now i have the example and can run it with the corresponding .py script stand alone.