[gem5-users] enum header file

2018-05-11 Thread Tariq Azmy
Some of cpu source codes include header files that begin with enum/.. such as: #include "enums/OpClass.hh" #include "enums/StaticInstFlags.hh" Where are these sources located so that I can see 'em? Thanks ___ gem5-users mailing list

[gem5-users] x86 floating point instruction

2018-05-23 Thread Tariq Azmy
Hi, I wrote simple code that does simple floating point multiplication and division operation and from the assembly, I can see there are MULSS and DIVSS instructions. But after I ran the simulation on gem5 and looked at the stat.txt, I can only see the entries in

Re: [gem5-users] x86 floating point instruction

2018-05-23 Thread Tariq Azmy
rinting a warning, but the fact that they don't actually do any math >> isn't impacting your program for whatever reason. I'll take a quick look. >> >> Gabe >> >> On Wed, May 23, 2018 at 2:07 PM, Tariq Azmy <tariqslaye...@gmail.com> >> wrote: >> >>

Re: [gem5-users] x86 floating point instruction

2018-05-25 Thread Tariq Azmy
a +1 or a +2 would be appropriate. > > Cheers, > Jason > > On Wed, May 23, 2018 at 5:56 PM Tariq Azmy <tariqslaye...@gmail.com> > wrote: > >> Thanks Gabe. Yeah it does not impact the program but it's just that the >> statistic is incorrect. >> >> By the way,

[gem5-users] Error when building gem5

2018-06-19 Thread Tariq Azmy
Hi, I got a fresh new gem5 from google repo ( https://gem5.googlesource.com/public/gem5) and built the X86 with scons. But there's an error from xbar: In file included from build/X86/mem/xbar.hh:57:0, from build/X86/mem/noncoherent_xbar.hh:54, from

Re: [gem5-users] x86 floating point instruction

2018-05-28 Thread Tariq Azmy
ason > > On Fri, May 25, 2018 at 2:12 PM Tariq Azmy > wrote: > >> Hi Gabe, Jason, >> >> Are those x86 SIMD SSE arithmetic instructions take only one cycle as >> latency? I looked into the FuncUnitConfig.py and seems like the op lats for >> the SIMD functional

[gem5-users] x86 instructions with microops

2018-05-29 Thread Tariq Azmy
Hi, How is a particular instruction being decoded, especially when it has micro-ops? I looked at the stats in commit_impl.hh if (!inst->isMicroop() || inst->isLastMicroop()) instsCommitted[tid]++; opsCommitted[tid]++; Does this means the micro ops is also stored as a Dynamic Inst, with

[gem5-users] Reading the size of X86 register

2018-06-05 Thread Tariq Azmy
Hi, Is there a way to access the data size of operand/destination register of some instruction? For example, in mediaOpReg, there are uint8_t srcSize, as well as uint8_t destSize but I believe these information don't get passed to the super class, i.e. StaticInst, when it get constructed.

Re: [gem5-users] Error when building gem5

2018-06-21 Thread Tariq Azmy
t need >> #include at the top of addr_range_map.hh. >> >> See https://gem5.googlesource.com/public/gem5/+/master/CONTRIBUTING.md >> for more details. >> >> Cheers, >> Jason >> >> On Tue, Jun 19, 2018 at 10:44 AM Tariq Azmy >> wr

[gem5-users] Running PARSEC Benchmark in SE Mode

2018-04-24 Thread Tariq Azmy
Hi all, There is a wiki page that describes how to run PARSEC benchmark on gem5, but it is built to run in FS mode. I wonder if anyone has tried running those benchmarks in SE mode? Thanks. ___ gem5-users mailing list gem5-users@gem5.org

Re: [gem5-users] Adding a new resource

2018-03-17 Thread Tariq Azmy
By "resources", I assume you are referring to each of the stage in the out-of-order pipeline? Those stages' implementation codes (fetch, decode, rename, etc..) are located inside the cpu/o3 directory. Branch prediction typically is done in fetch stage, so if you look inside the fetch.hh source