[gem5-users] Does GEM5 support running applications compiled with target mcpu = cortex-m4?

Hi , I was trying to run the hello world example on GEM5 whose source file was compiled using: **arm-linux-gnueabi-gcc -mtune=cortex-m4 -mcpu=cortex-m4 --static -march=armv7e-m -mthumb hello.c -o hello_32** And when i try to run it on GEM5, i get the following: **./build/ARM/gem5.opt

[gem5-users] ARM - syscall read still needs retry issue - how to fix it?

Hi, When i am running dhrystone benchmark on arm model, it never gets completed. so i put the debug flags and i could see: **`2821960548: system.cpu_cluster.cpus: T0 : syscall read still needs retry.`** **`2821960548: read.wrapped_function_event: EventFunctionWrapped 83716 scheduled @

[gem5-users] riscv simulation doesnt get completed - syscall read still needs retry

Hi , I am trying to run dhrystone on riscv. The number of Loops/Runs = 10. Once i start the run, it doesnt get completed. No error was thrown either: ./build/RISCV/gem5.opt ./configs/example/se.py -c ./tests/dhrystone_riscv_u74 gem5 Simulator System. http://gem5.org gem5 is copyrighted

[gem5-users] Re: riscv simulation doesnt get completed - syscall read still needs retry

Hi , Have anyone come across this issue? Any suggestion on the fix would be greatly appreciated. Regards, Tom ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] Re: The ARM model simulation is failing when i add "All" debug flag

Hi Kaustav Goswami, Thanks a lot. It worked. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] fatal: Syscall 278 out of range (ARM) - can i skip/supress syscall unimplemeted errors

Hi All, I am trying to run dhrystone benchmark on ARM and i get the following: ./build/ARM/gem5.opt --debug-flags=Exec --debug-file=dhrystone_10k_a77_trace ./configs/example/arm/starter_se.py --cpu minor --cpu-freq 3.0GHz --mem-type DDR4_2400_8x8 ./tests/dhrystone_10k gem5 Simulator System.

[gem5-users] Re: svc Instruction

Hi V Vanchinathan, Hope you are doing well. I came across the same doubt. Were you able to find the explanation for the same? Regards, Tom ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] Re: Doubt on the ARM exec trace results when compared with disassembly of the executable

Hi Giacomo, Thank you very much for your kind response. I greatly appreciate it. Wishing you a great day. Meet again later. Tom ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] Re: ARM model - load instruction reads non-zero data from an address which was not written out prior (as per traces)

Hi Gabe, Thank you very much for the response. I greatly appreciate it. I was using just the -d flag for getting the objdump. Now i tried using additional flags and used a parser to get the addresses and data present within. I was able to get around 121 of the addresses which were having the

[gem5-users] Re: How does an out of order pipeline implementation handle instructions (cmp, adds,cmn etc.) which update N,Z,C,V?

Hello Jason, Thank you very much for the quick response. I greatly appreciate it. I will check the source code mentioned. Wishing you a great day. Regards, Tom ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to

[gem5-users] Re: x86 instructions with microops

Hi Tariq Azmy, Were you able to get more information on the original question that you had asked? Especially the file which has the list of all supported microops per arch? Regards, Tom ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe

[gem5-users] Re: ARM model - load instruction reads non-zero data from an address which was not written out prior (as per traces)

Hi , I have attached a shorter Exec trace to this message. If we look at lines: line 4: ldr x1, [sp]: MemRead : D=0x0001 A=0x7efe70 line 74 : ldr x1, [x0]: MemRead : D=0x0010 A=0x7efe90 line 88 : ldr x3, [x8,

[gem5-users] Re: Issue with strange virtual address access

Hi Jason, Thank you very much for your swift response. I hugely appreciate it. Wishing you a great day. Regards, Tom ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] How does an out of order pipeline implementation handle instructions (cmp, adds,cmn etc.) which update N,Z,C,V?

Hi , This may sound very generic, but i want to try some experiments with the out of order implementation. I came across few scenarios, which are listed below (any input would be helpful): 1. lets consider the following set of instructions (an example which was made up): Address instr

[gem5-users] Re: Issue with strange virtual address access

Hi Jason, I have one doubt. The following is some selected parts of Exec trace: If we look at lines: line 4: ldr x1, [sp]: MemRead : D=0x0001 A=0x7efe70 line 74 : ldr x1, [x0]: MemRead : D=0x0010 A=0x7efe90 line 88 :

[gem5-users] The ARM model simulation is failing when i add "All" debug flag

The terminal contents are as follows: ./build/ARM/gem5.opt --debug-flags=All --debug-file=All_Debug configs/example/se.py --cpu-type=O3CPU --caches -c /home/tom/Documents/gem5/tests/test-progs/hello/bin/arm/linux/hello gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use