[gem5-users] Re: A puzzle about how TLB is emulated
Hi Jason & Nathanael, Thank you for both of your informative replies. These have been really helpful. Leon ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: A puzzle about how TLB is emulated
Hi Jason, Thank you for such elaborate explanation. I will look into it. Another weird thing happened today. I noticed that while running a benchmark, TLB seemed to have never triggered a miss condition. I came to this conclusion because TLB always started and ended at the same tick according to my console (my printfs' doing), even for the first few entries since real simulation. Does this seem natural to you? Should I, in your view, run the benchmark much longer and then, like, redirect the output into a file to analyze the tick difference? Or maybe I misoperated something? Looking forward to your reply! Leon ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: A puzzle about how TLB is emulated
Hello, Although not modelled, they do have an impact on performance for the O3 model. Upon a TLB miss, the access is considered as faulty, triggering a pipeline flush and a re-execution. At that point, the SE page table has been populated and the access gets its translation. Also, I assume that the TLB hit latency is not modelled as it happens in parallel to the L1 cache access. But this assumption only hold if your cache access latency Is higher than the TLB hit latency (which is usually the case). Thanks, Nathanael From: Jason Lowe-Power via gem5-users [mailto:gem5-users@gem5.org] Sent: Thursday, April 22, 2021 10:12 PM To: gem5 users mailing list Cc: Θοδωρής Τροχάτος ; Jason Lowe-Power Subject: [gem5-users] Re: A puzzle about how TLB is emulated Hello, As far as I know, TLB misses are not modeled in SE mode at all. Cheers, Jason On Thu, Apr 22, 2021 at 12:50 PM Θοδωρής Τροχάτος via gem5-users mailto:gem5-users@gem5.org>> wrote: Hi Jason! Thanks for the info! Do you know what is happening when there is a TLB miss in SE mode? Is the latency of a TLB miss modeled in some way in SE? ___ gem5-users mailing list -- gem5-users@gem5.org<mailto:gem5-users@gem5.org> To unsubscribe send an email to gem5-users-le...@gem5.org<mailto:gem5-users-le...@gem5.org> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: A puzzle about how TLB is emulated
Hello, As far as I know, TLB misses are not modeled in SE mode at all. Cheers, Jason On Thu, Apr 22, 2021 at 12:50 PM Θοδωρής Τροχάτος via gem5-users < gem5-users@gem5.org> wrote: > Hi Jason! Thanks for the info! > > Do you know what is happening when there is a TLB miss in SE mode? > Is the latency of a TLB miss modeled in some way in SE? > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: A puzzle about how TLB is emulated
Hi Jason! Thanks for the info! Do you know what is happening when there is a TLB miss in SE mode? Is the latency of a TLB miss modeled in some way in SE? ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: A puzzle about how TLB is emulated
Hi Leon,
I believe you're correct. When there is a TLB hit, it's up to the *CPU
model* to model the latency of the TLB access. I think this implementation
was designed this way to give flexibility to the CPU models. Since the TLB
is deeply embedded in the pipeline, we wouldn't want to always have a 1
cycle latency for the TLB. On the other hand, when there is a miss (in FS
mode), the page table walker will model the correct delay.
Cheers,
Jason
On Wed, Apr 21, 2021 at 6:38 AM Leon Zhao via gem5-users <
gem5-users@gem5.org> wrote:
> Hi all,
>
> While I'm doing some research about how TLB is emulated in gem5 the other
> day, I noticed that TLB costs no ticks, which is quite unusual.
> I tried printing current tick before and after (xxx is where I set in my
> print declaration):
> (1) src/cpu/o3/lsq_impl.hh
> void LSQ::LSQRequest::sendFragmentToTranslation(int i) {
> xxx
> the original function body
> xxx
> }
> (2) src/cpu/o3/fetch_impl.hh
> DefaultFetch::finishTranslation(const Fault , const
> RequestPtr _req) {
> ...
> xxx
> if (fault == NoFault) {
>
> fetchedCacheLines++;
> xxx
> ...
> }
> ...
> }
>
> However, in both cases, both print functions printed the same tick number
> (starting from the very beginning). Is this normal or I found the wrong
> places to implant printf's or there's some misunderstanding about my
> perspective?
>
> Here is a sample of what's left on my console:
>
> !>> TLB starts @ tick=86592000
> !>> TLB ends @ tick=86592000
> !>> TLB starts @ tick=86593000
> !>> TLB ends @ tick=86593000
> !>> TLB starts @ tick=86597000
> !>> TLB ends @ tick=86597000
>
> Any pointers would do. Thanks in advance.
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