[gem5-users] Re: Multi-level TLB is implemented in performance

2023-05-18 Thread Arun Kavumkal via gem5-users
Thanks for your email.
I will look into the "multi-level TLB for Arm" implementation

Wish you a good day
Arun


On Thu, May 18, 2023 at 9:25 PM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:

> Just for the sake of completeness (I know Arun asked about X86).
> There is a multi-level TLB for Arm; it is possible for other ISAs to
> implement the same, it requires a developer to move the
> translateAtomic/Timing methods from the TLB to the MMU
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
> *From: *Jason Lowe-Power via gem5-users 
> *Date: *Thursday, 18 May 2023 at 16:38
> *To: *The gem5 Users mailing list 
> *Cc: *Laney Laney <522808...@qq.com>, Arun Kavumkal <
> arunkp.onl...@gmail.com>, Jason Lowe-Power 
> *Subject: *[gem5-users] Re: Multi-level TLB is implemented in performance
>
> There is not a multi-level TLB model in mainline gem5.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Thu, May 18, 2023 at 5:43 AM Arun Kavumkal via gem5-users <
> gem5-users@gem5.org> wrote:
>
> Hi,
>
> Can anyone please tell me whether a multi-level TLB implementation is
> currently available for x86?
>
>
>
> Thanks
>
> Arun
>
>
>
> On Wed, Oct 28, 2020 at 9:01 PM Jason Lowe-Power via gem5-users <
> gem5-users@gem5.org> wrote:
>
> Yes, this is possible, and I believe it's already implemented for Arm.
>
>
>
> The best place to start is src/arch//tlb.cc
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Wed, Oct 28, 2020 at 1:27 AM Laney Laney via gem5-users <
> gem5-users@gem5.org> wrote:
>
> Hi,all. I would like to know if it is possible to implement multi-level
> TLB on gem5 performance by modeling the latency of TLB. If so, which files
> or functions should I start with?
> ___
> gem5-users mailing list -- gem5-users@gem5.org
> To unsubscribe send an email to gem5-users-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
> ___
> gem5-users mailing list -- gem5-users@gem5.org
> To unsubscribe send an email to gem5-users-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
> ___
> gem5-users mailing list -- gem5-users@gem5.org
> To unsubscribe send an email to gem5-users-le...@gem5.org
>
> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
>
___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org


[gem5-users] Re: Multi-level TLB is implemented in performance

2023-05-18 Thread Giacomo Travaglini via gem5-users
Just for the sake of completeness (I know Arun asked about X86).
There is a multi-level TLB for Arm; it is possible for other ISAs to implement 
the same, it requires a developer to move the translateAtomic/Timing methods 
from the TLB to the MMU

Kind Regards

Giacomo

From: Jason Lowe-Power via gem5-users 
Date: Thursday, 18 May 2023 at 16:38
To: The gem5 Users mailing list 
Cc: Laney Laney <522808...@qq.com>, Arun Kavumkal , 
Jason Lowe-Power 
Subject: [gem5-users] Re: Multi-level TLB is implemented in performance
There is not a multi-level TLB model in mainline gem5.

Cheers,
Jason

On Thu, May 18, 2023 at 5:43 AM Arun Kavumkal via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi,
Can anyone please tell me whether a multi-level TLB implementation is currently 
available for x86?

Thanks
Arun

On Wed, Oct 28, 2020 at 9:01 PM Jason Lowe-Power via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Yes, this is possible, and I believe it's already implemented for Arm.

The best place to start is src/arch//tlb.cc

Cheers,
Jason

On Wed, Oct 28, 2020 at 1:27 AM Laney Laney via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi,all. I would like to know if it is possible to implement multi-level TLB on 
gem5 performance by modeling the latency of TLB. If so, which files or 
functions should I start with?
___
gem5-users mailing list -- gem5-users@gem5.org<mailto:gem5-users@gem5.org>
To unsubscribe send an email to 
gem5-users-le...@gem5.org<mailto:gem5-users-le...@gem5.org>
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
___
gem5-users mailing list -- gem5-users@gem5.org<mailto:gem5-users@gem5.org>
To unsubscribe send an email to 
gem5-users-le...@gem5.org<mailto:gem5-users-le...@gem5.org>
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
___
gem5-users mailing list -- gem5-users@gem5.org<mailto:gem5-users@gem5.org>
To unsubscribe send an email to 
gem5-users-le...@gem5.org<mailto:gem5-users-le...@gem5.org>
IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.
___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org


[gem5-users] Re: Multi-level TLB is implemented in performance

2023-05-18 Thread Jason Lowe-Power via gem5-users
There is not a multi-level TLB model in mainline gem5.

Cheers,
Jason

On Thu, May 18, 2023 at 5:43 AM Arun Kavumkal via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
> Can anyone please tell me whether a multi-level TLB implementation is
> currently available for x86?
>
> Thanks
> Arun
>
> On Wed, Oct 28, 2020 at 9:01 PM Jason Lowe-Power via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Yes, this is possible, and I believe it's already implemented for Arm.
>>
>> The best place to start is src/arch//tlb.cc
>>
>> Cheers,
>> Jason
>>
>> On Wed, Oct 28, 2020 at 1:27 AM Laney Laney via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi,all. I would like to know if it is possible to implement multi-level
>>> TLB on gem5 performance by modeling the latency of TLB. If so, which files
>>> or functions should I start with?
>>> ___
>>> gem5-users mailing list -- gem5-users@gem5.org
>>> To unsubscribe send an email to gem5-users-le...@gem5.org
>>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>>>
>> ___
>> gem5-users mailing list -- gem5-users@gem5.org
>> To unsubscribe send an email to gem5-users-le...@gem5.org
>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
> ___
> gem5-users mailing list -- gem5-users@gem5.org
> To unsubscribe send an email to gem5-users-le...@gem5.org
>
___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org


[gem5-users] Re: Multi-level TLB is implemented in performance

2023-05-18 Thread Arun Kavumkal via gem5-users
Hi,
Can anyone please tell me whether a multi-level TLB implementation is
currently available for x86?

Thanks
Arun

On Wed, Oct 28, 2020 at 9:01 PM Jason Lowe-Power via gem5-users <
gem5-users@gem5.org> wrote:

> Yes, this is possible, and I believe it's already implemented for Arm.
>
> The best place to start is src/arch//tlb.cc
>
> Cheers,
> Jason
>
> On Wed, Oct 28, 2020 at 1:27 AM Laney Laney via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi,all. I would like to know if it is possible to implement multi-level
>> TLB on gem5 performance by modeling the latency of TLB. If so, which files
>> or functions should I start with?
>> ___
>> gem5-users mailing list -- gem5-users@gem5.org
>> To unsubscribe send an email to gem5-users-le...@gem5.org
>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>>
> ___
> gem5-users mailing list -- gem5-users@gem5.org
> To unsubscribe send an email to gem5-users-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org


[gem5-users] Re: Multi-level TLB is implemented in performance

2020-10-28 Thread Jason Lowe-Power via gem5-users
Yes, this is possible, and I believe it's already implemented for Arm.

The best place to start is src/arch//tlb.cc

Cheers,
Jason

On Wed, Oct 28, 2020 at 1:27 AM Laney Laney via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,all. I would like to know if it is possible to implement multi-level
> TLB on gem5 performance by modeling the latency of TLB. If so, which files
> or functions should I start with?
> ___
> gem5-users mailing list -- gem5-users@gem5.org
> To unsubscribe send an email to gem5-users-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s