Hallo,

at the moment i try to create vector ports. I used: 
http://learning.gem5.org/book/part2/simplecache.html to get an idea how to do 
this, but the example is not working. The implemented port is still not a 
vector port.


What i have is:


declaration inside the header:


    std::vector<CPUSidePort*> l1iPort;
    std::vector<CPUSidePort*> l1dPort;


the getSlavePort method:


    BaseSlavePort&

    Dapu::getSlavePort(const std::string& if_name, PortID idx)

    {

        if (if_name == "L1i_port" && idx < l1iPort.size()) {
            return *l1iPort[idx];
        }
        else if (if_name == "L1d_port" && idx < l1dPort.size()) {
            return *l1dPort[idx];
        }
        else if (if_name == "L2_port"){
            return l2Port;
        }
        else {
            return MemObject::getSlavePort(if_name, idx);
        }
   }


At the moment the problem is the initialization inside the contructor:


    for (int i = 0; i < p->cpu_count; ++i) {
        l1iPort.emplace_back(name() + csprintf(".L1i_port[%d]", i), i, this);
        l1dPort.emplace_back(name() + csprintf(".L1d_port[%d]", i), i, this);
    }


this is not working and i find no answer inside the gem5 code how to do this 
properly. I tried to trace back the approach inside the xbar.cc/hh but the 
initialization is missing. I would appreciate your help.


regards,

Markus Neu
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