Re: [gem5-users] Issue with creation of L3 Cache (and tol3bus)

That helped a bunch. Thank you very much for your help. -Brian Suchy From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Jason Lowe-Power Sent: Saturday, February 4, 2017 11:28 AM To: gem5 users mailing list Subject: Re: [gem5-users] Issue with creation of

Re: [gem5-users] Issue with creation of L3 Cache (and tol3bus)

This is hard to understand what's going on, but I'll try: The error is "AttributeError: object 'O3_ARM_v7a_3' has no attribute 'tol3bus'". This means that you are referencing the variable tol3bus before it is defined. Did you add this variable to the ARM CPU? It would probably make more sense for

Re: [gem5-users] Issue with creation of L3 Cache (and tol3bus)

Here are the differences between the files: O3_ARM_v7a,py: >class O3_ARM_v7aL3(Cache): > tag_latency = 20 > data_latency = 20 > response_latency = 20 > mshrs = 512 > tgts_per_mshr = 20 > size = '2MB' > assoc = 16 > write_buffers = 256 > clusivity = 'mostly_excl' >class

Re: [gem5-users] Issue with creation of L3 Cache (and tol3bus)

Hello Brian Suchy, its really hard to see code like this. maybe you should do a diff file? also, i did two patches some time ago to have some new L2 configurations they may be of help for you look here: http://reviews.gem5.org/r/3495/ http://reviews.gem5.org/r/3506/ On Fri, Feb 3, 2017 at 6:05