Re: [gem5-users] Issue with creation of L3 Cache (and tol3bus)

[Suchy, Brian]

That helped a bunch. Thank you very much for your help.

-Brian Suchy

From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Jason 
Lowe-Power
Sent: Saturday, February 4, 2017 11:28 AM
To: gem5 users mailing list 
Subject: Re: [gem5-users] Issue with creation of L3 Cache (and tol3bus)

This is hard to understand what's going on, but I'll try:

The error is "AttributeError: object 'O3_ARM_v7a_3' has no attribute 
'tol3bus'". This means that you are referencing the variable tol3bus before it 
is defined. Did you add this variable to the ARM CPU? It would probably make 
more sense for the L3 bus to be part of the system anyway. Here's a (not 
perfect) example of how to create an L3 cache with the classic memory system: 
https://github.com/powerjg/gem5/blob/devel/simplefs/configs/myconfigs/system/caches.py.
 You may be able to use this as a guide.

Cheers,
Jason

On Sat, Feb 4, 2017 at 6:41 AM Suchy, Brian 
> wrote:

Here are the differences between the files:

O3_ARM_v7a,py:





>class O3_ARM_v7aL3(Cache):
>  tag_latency = 20
>   data_latency = 20
>   response_latency = 20
>   mshrs = 512
>   tgts_per_mshr = 20
>   size = '2MB'
>   assoc = 16
>   write_buffers = 256
>   clusivity = 'mostly_excl'


>class O3_ARM_v7aV(Cache):
>   tag_latency = 2
>   data_latency = 2
>   response_latency = 2
>   mshrs = 6
>   tgts_per_mshr = 20
>   size = '16kB'
>   assoc = 1
>   write_buffers = 256
>   writeback_clean = True


CacheConfig.py:
> from O3_ARM_v7a import *
49c50
< if options.external_memory_system and (options.caches or options.l2cache):
---

> if options.external_memory_system and (options.caches or options.l2cache 
> or options.l3cache or options.vcache):
56,71d56



< if options.cpu_type == "arm_detailed":
< try:
< from O3_ARM_v7a import *
< except:

< print "arm_detailed is unavailable. Did you compile the O3 model?"
< sys.exit(1)
<
< dcache_class, icache_class, l2_cache_class, walk_cache_class = \
< O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \
< O3_ARM_v7aWalkCache
< else:
< dcache_class, icache_class, l2_cache_class, walk_cache_class = \
< L1_DCache, L1_ICache, L2Cache, None

<
< if buildEnv['TARGET_ISA'] == 'x86':
< walk_cache_class = PageTableWalkerCache
82a68,85


>
> if options.cpu_type == "arm_detailed":

> dcache_class, icache_class, l2_cache_class, l3_cache_class, 
> v_cache_class, walk_cache_class = \
> O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, O3_ARM_v7aL3, 
> O3_ARM_v7aV, \
> O3_ARM_v7aWalkCache
> else:
> dcache_class, icache_class, l2_cache_class, l3_cache_class, 
> v_cache_class, walk_cache_class = \
> L1_DCache, L1_ICache, L2Cache, L3Cache, VCache, None
>
> if buildEnv['TARGET_ISA'] == 'x86':
> walk_cache_class = PageTableWalkerCache
>
93a97,110



> #Added L3 and VCache
> if options.l3cache:
>system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain, 
> size=options.l3_size,assoc=options.l3_assoc)
>
>system.tol3bus = L2XBar(clk_domain = system.cpu_clk_domain)
>system.l3.cpu_side = system.tol3bus.master
>system.l3.mem_side = system.membus.slave
> #
> if options.vcache:
>system.v = v_cache_class(clk_domain=system.cpu_clk_domain, 
> size=options.v_size,assoc=options.v_assoc)
>system.tovbus = L2XBar(clk_domain = system.cpu_clk_domain)
>system.v.cpu_side = system.tovbus.master
>system.v.mem_side = system.membus.slave
>
103a121,134

> #Added L3 and VCache Options
> if options.l3cache:
>   system.cpu[i].l2 = l2_cache_class(size=options.l2_size, 
> assoc=options.l2_assoc)
>   system.cpu[i].tol2bus = L2XBar(clk_domain = 
> system.cpu_clk_domain)
>   system.cpu[i].l2.cpu_side = system.cpu[i].tol2bus.master
>   system.cpu[i].l2.mem_side = system.tol3bus.slave
>
>
> if options.vcache:
> system.cpu[i].l3 = l3_cache_class(size=options.l3_size, 
> assoc=options.l3_assoc)
> system.cpu[i].tol3bus = L2XBar(clk_domain = 
> system.cpu_clk_domain)
> system.cpu[i].l3.cpu_side = system.cpu[i].tol3bus.master
> system.cpu[i].l3.mem_side = system.tovbus.slave
>
158,161c189,192



< if options.l2cache:
< system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
< elif options.external_memory_system:
< system.cpu[i].connectUncachedPorts(system.membus)
---

> if options.vcache:
> system.cpu[i].connectAllPorts(system.cpu[i].tovbus, system.membus)
>
163c194,204


< system.cpu[i].connectAllPorts(system.membus)
---

> if options.l3cache:
> 

Re: [gem5-users] Issue with creation of L3 Cache (and tol3bus)

[Jason Lowe-Power]

This is hard to understand what's going on, but I'll try:

The error is "AttributeError: object 'O3_ARM_v7a_3' has no attribute
'tol3bus'". This means that you are referencing the variable tol3bus before
it is defined. Did you add this variable to the ARM CPU? It would probably
make more sense for the L3 bus to be part of the system anyway. Here's a
(not perfect) example of how to create an L3 cache with the classic memory
system:
https://github.com/powerjg/gem5/blob/devel/simplefs/configs/myconfigs/system/caches.py.
You may be able to use this as a guide.

Cheers,
Jason

On Sat, Feb 4, 2017 at 6:41 AM Suchy, Brian  wrote:

> Here are the differences between the files:
>
> O3_ARM_v7a,py:
>
>
>
>
> >class O3_ARM_v7aL3(Cache):
> >  tag_latency = 20
> >   data_latency = 20
> >   response_latency = 20
> >   mshrs = 512
> >   tgts_per_mshr = 20
> >   size = '2MB'
> >   assoc = 16
> >   write_buffers = 256
> >   clusivity = 'mostly_excl'
>
>
> >class O3_ARM_v7aV(Cache):
> >   tag_latency = 2
> >   data_latency = 2
> >   response_latency = 2
> >   mshrs = 6
> >   tgts_per_mshr = 20
> >   size = '16kB'
> >   assoc = 1
> >   write_buffers = 256
> >   writeback_clean = True
>
>
> CacheConfig.py:
> > from O3_ARM_v7a import *
> 49c50
> < if options.external_memory_system and (options.caches or
> options.l2cache):
> ---
>
> > if options.external_memory_system and (options.caches or
> options.l2cache or options.l3cache or options.vcache):
> 56,71d56
>
>
>
> < if options.cpu_type == "arm_detailed":
> < try:
> < from O3_ARM_v7a import *
> < except:
>
> < print "arm_detailed is unavailable. Did you compile the O3
> model?"
> < sys.exit(1)
> <
> < dcache_class, icache_class, l2_cache_class, walk_cache_class = \
> < O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \
> < O3_ARM_v7aWalkCache
> < else:
> < dcache_class, icache_class, l2_cache_class, walk_cache_class = \
> < L1_DCache, L1_ICache, L2Cache, None
>
> <
> < if buildEnv['TARGET_ISA'] == 'x86':
> < walk_cache_class = PageTableWalkerCache
> 82a68,85
>
>
> >
> > if options.cpu_type == "arm_detailed":
>
> > dcache_class, icache_class, l2_cache_class, l3_cache_class,
> v_cache_class, walk_cache_class = \
> > O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2,
> O3_ARM_v7aL3, O3_ARM_v7aV, \
> > O3_ARM_v7aWalkCache
> > else:
> > dcache_class, icache_class, l2_cache_class, l3_cache_class,
> v_cache_class, walk_cache_class = \
> > L1_DCache, L1_ICache, L2Cache, L3Cache, VCache, None
> >
> > if buildEnv['TARGET_ISA'] == 'x86':
> > walk_cache_class = PageTableWalkerCache
> >
> 93a97,110
>
>
>
> > #Added L3 and VCache
> > if options.l3cache:
> >system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain,
> size=options.l3_size,assoc=options.l3_assoc)
> >
> >system.tol3bus = L2XBar(clk_domain = system.cpu_clk_domain)
> >system.l3.cpu_side = system.tol3bus.master
> >system.l3.mem_side = system.membus.slave
> > #
> > if options.vcache:
> >system.v = v_cache_class(clk_domain=system.cpu_clk_domain,
> size=options.v_size,assoc=options.v_assoc)
> >system.tovbus = L2XBar(clk_domain = system.cpu_clk_domain)
> >system.v.cpu_side = system.tovbus.master
> >system.v.mem_side = system.membus.slave
> >
> 103a121,134
>
> > #Added L3 and VCache Options
> > if options.l3cache:
> >   system.cpu[i].l2 = l2_cache_class(size=options.l2_size,
> assoc=options.l2_assoc)
> >   system.cpu[i].tol2bus = L2XBar(clk_domain =
> system.cpu_clk_domain)
> >   system.cpu[i].l2.cpu_side = system.cpu[i].tol2bus.master
> >   system.cpu[i].l2.mem_side = system.tol3bus.slave
> >
> >
> > if options.vcache:
> > system.cpu[i].l3 = l3_cache_class(size=options.l3_size,
> assoc=options.l3_assoc)
> > system.cpu[i].tol3bus = L2XBar(clk_domain =
> system.cpu_clk_domain)
> > system.cpu[i].l3.cpu_side = system.cpu[i].tol3bus.master
> > system.cpu[i].l3.mem_side = system.tovbus.slave
> >
> 158,161c189,192
>
>
>
> < if options.l2cache:
> < system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
> < elif options.external_memory_system:
> < system.cpu[i].connectUncachedPorts(system.membus)
> ---
>
> > if options.vcache:
> > system.cpu[i].connectAllPorts(system.cpu[i].tovbus,
> system.membus)
> >
> 163c194,204
>
>
> < system.cpu[i].connectAllPorts(system.membus)
> ---
>
> > if options.l3cache:
> > system.cpu[i].connectAllPorts(system.cpu[i].tol3bus,
> system.membus)
> > else:
> > if options.l2cache:
> > 

Re: [gem5-users] Issue with creation of L3 Cache (and tol3bus)

[Suchy, Brian]

Here are the differences between the files:

O3_ARM_v7a,py:




>class O3_ARM_v7aL3(Cache):
>  tag_latency = 20
>   data_latency = 20
>   response_latency = 20
>   mshrs = 512
>   tgts_per_mshr = 20
>   size = '2MB'
>   assoc = 16
>   write_buffers = 256
>   clusivity = 'mostly_excl'

>class O3_ARM_v7aV(Cache):
>   tag_latency = 2
>   data_latency = 2
>   response_latency = 2
>   mshrs = 6
>   tgts_per_mshr = 20
>   size = '16kB'
>   assoc = 1
>   write_buffers = 256
>   writeback_clean = True


CacheConfig.py:
> from O3_ARM_v7a import *
49c50
< if options.external_memory_system and (options.caches or options.l2cache):
---
> if options.external_memory_system and (options.caches or options.l2cache 
> or options.l3cache or options.vcache):
56,71d56



< if options.cpu_type == "arm_detailed":
< try:
< from O3_ARM_v7a import *
< except:
< print "arm_detailed is unavailable. Did you compile the O3 model?"
< sys.exit(1)
<
< dcache_class, icache_class, l2_cache_class, walk_cache_class = \
< O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \
< O3_ARM_v7aWalkCache
< else:
< dcache_class, icache_class, l2_cache_class, walk_cache_class = \
< L1_DCache, L1_ICache, L2Cache, None
<
< if buildEnv['TARGET_ISA'] == 'x86':
< walk_cache_class = PageTableWalkerCache
82a68,85


>
> if options.cpu_type == "arm_detailed":
> dcache_class, icache_class, l2_cache_class, l3_cache_class, 
> v_cache_class, walk_cache_class = \
> O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, O3_ARM_v7aL3, 
> O3_ARM_v7aV, \
> O3_ARM_v7aWalkCache
> else:
> dcache_class, icache_class, l2_cache_class, l3_cache_class, 
> v_cache_class, walk_cache_class = \
> L1_DCache, L1_ICache, L2Cache, L3Cache, VCache, None
>
> if buildEnv['TARGET_ISA'] == 'x86':
> walk_cache_class = PageTableWalkerCache
>
93a97,110


> #Added L3 and VCache
> if options.l3cache:
>system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain, 
> size=options.l3_size,assoc=options.l3_assoc)
>
>system.tol3bus = L2XBar(clk_domain = system.cpu_clk_domain)
>system.l3.cpu_side = system.tol3bus.master
>system.l3.mem_side = system.membus.slave
> #
> if options.vcache:
>system.v = v_cache_class(clk_domain=system.cpu_clk_domain, 
> size=options.v_size,assoc=options.v_assoc)
>system.tovbus = L2XBar(clk_domain = system.cpu_clk_domain)
>system.v.cpu_side = system.tovbus.master
>system.v.mem_side = system.membus.slave
>
103a121,134
> #Added L3 and VCache Options
> if options.l3cache:
>   system.cpu[i].l2 = l2_cache_class(size=options.l2_size, 
> assoc=options.l2_assoc)
>   system.cpu[i].tol2bus = L2XBar(clk_domain = 
> system.cpu_clk_domain)
>   system.cpu[i].l2.cpu_side = system.cpu[i].tol2bus.master
>   system.cpu[i].l2.mem_side = system.tol3bus.slave
>
>
> if options.vcache:
> system.cpu[i].l3 = l3_cache_class(size=options.l3_size, 
> assoc=options.l3_assoc)
> system.cpu[i].tol3bus = L2XBar(clk_domain = 
> system.cpu_clk_domain)
> system.cpu[i].l3.cpu_side = system.cpu[i].tol3bus.master
> system.cpu[i].l3.mem_side = system.tovbus.slave
>
158,161c189,192


< if options.l2cache:
< system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
< elif options.external_memory_system:
< system.cpu[i].connectUncachedPorts(system.membus)
---
> if options.vcache:
> system.cpu[i].connectAllPorts(system.cpu[i].tovbus, system.membus)
>
163c194,204


< system.cpu[i].connectAllPorts(system.membus)
---
> if options.l3cache:
> system.cpu[i].connectAllPorts(system.cpu[i].tol3bus, 
> system.membus)
> else:
> if options.l2cache:
> system.cpu[i].connectAllPorts(system.tol2bus, 
> system.membus)
> else:
> if options.external_memory_system:
> system.cpu[i].connectUncachedPorts(system.membus)
> else:
> system.cpu[i].connectAllPorts(system.membus)
186c227

< return make
---
> return make


Does this help out? Thank you again for your help.

-Brian Suchy





From: gem5-users  on behalf of Rodrigo Cataldo 

Sent: Friday, February 3, 2017 5:15 AM
To: gem5 users mailing list
Subject: Re: [gem5-users] Issue with creation of L3 Cache (and tol3bus)

Hello Brian Suchy,
its really hard to see code like this.
maybe you should do a diff file?

also, i did two patches some time ago to have some new L2 configurations
they may be of help for you
look here:

Re: [gem5-users] Issue with creation of L3 Cache (and tol3bus)

[Rodrigo Cataldo]

Hello Brian Suchy,
its really hard to see code like this.
maybe you should do a diff file?

also, i did two patches some time ago to have some new L2 configurations
they may be of help for you
look here:
http://reviews.gem5.org/r/3495/
http://reviews.gem5.org/r/3506/


On Fri, Feb 3, 2017 at 6:05 AM, Suchy, Brian  wrote:

> Hello everyone,
>
>
> I am attempting to create an L3 cache to run in FS mode with the ARM
> detailed processor; however, I am encountering an error when trying to run
> the simulator. When I try run the simulator, the following occurs:
>
>
> --BEGIN TERMINAL--
>
>
> $:~/Documents/gem5/gem5$ sudo build/ARM/gem5.opt configs/example/fs.py
> --kernel=/home/suchy/Documents/gem5/gem5/Benchmark/asimBenchmark/binaries/
> vmlinux.smp.ics.arm.asimbench.2.6.35 --dtb-file=/home/suchy/
> Documents/gem5/gem5/Benchmark/asimBenchmark/binaries/vexpress-v2p-ca15-tc1.dtb
> --disk-image=/home/suchy/Documents/gem5/gem5/Benchmark/
> asimBenchmark/disks/ARMv7a-ICS-Android.SMP.Asimbench-v3.img
> --script=/home/suchy/Documents/gem5/gem5/Benchmark/
> asimBenchmark/scripts/ttpod.rcS --os-type=android-ics --mem-size=256MB
> --machine-type=RealView_PBX --caches --l3cache
> gem5 Simulator System.  http://gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 compiled Feb  2 2017 23:49:17
> gem5 started Feb  2 2017 23:56:43
> gem5 executing on SmallButMIghty, pid 11798
> command line: build/ARM/gem5.opt configs/example/fs.py
> --kernel=/home/suchy/Documents/gem5/gem5/Benchmark/asimBenchmark/binaries/
> vmlinux.smp.ics.arm.asimbench.2.6.35 --dtb-file=/home/suchy/
> Documents/gem5/gem5/Benchmark/asimBenchmark/binaries/vexpress-v2p-ca15-tc1.dtb
> --disk-image=/home/suchy/Documents/gem5/gem5/Benchmark/
> asimBenchmark/disks/ARMv7a-ICS-Android.SMP.Asimbench-v3.img
> --script=/home/suchy/Documents/gem5/gem5/Benchmark/
> asimBenchmark/scripts/ttpod.rcS --os-type=android-ics --mem-size=256MB
> --machine-type=RealView_PBX --caches --l3cache
>
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "/home/suchy/Documents/gem5/gem5/src/python/m5/main.py", line 400,
> in main
> exec filecode in scope
>   File "configs/example/fs.py", line 341, in 
> test_sys = build_test_system(np)
>   File "configs/example/fs.py", line 230, in build_test_system
> CacheConfig.config_cache(options, test_sys)
>   File "/home/suchy/Documents/gem5/gem5/configs/common/CacheConfig.py",
> line 195, in config_cache
> system.cpu[i].connectAllPorts(system.cpu[i].tol3bus, system.membus)
>   File "/home/suchy/Documents/gem5/gem5/src/python/m5/SimObject.py", line
> 1095, in __getattr__
> raise AttributeError, err_string
> AttributeError: object 'O3_ARM_v7a_3' has no attribute 'tol3bus'
>   (C++ object is not yet constructed, so wrapped C++ methods are
> unavailable.)
>
> --END TERMINAL--
>
> I cannot track down where I go about adding the tol3bus to get past this
> stage. Is there anyone who can recommend where to look? Also, I have my
> default processor set to detailed_arm.
>
> The following are also my CacheConfig.Py, O3_ARM-V7a.Py, and Caches.Py
> files:
> Side note: I am also trying to create a victim cache, but it encounters
> the same issue. SO if you see a vcache or anything like that, please feel
> free to ignore it
>
> --Begin CacheConfig.Py--
>
>
> import m5
> from m5.objects import *
> from Caches import *
> from O3_ARM_v7a import *
>
> def config_cache(options, system):
> if options.external_memory_system and (options.caches or
> options.l2cache or options.l3cache or options.vcache):
> print "External caches and internal caches are exclusive
> options.\n"
> sys.exit(1)
>
> if options.external_memory_system:
> ExternalCache = ExternalCacheFactory(options.
> external_memory_system)
>
>
> # Set the cache line size of the system
> system.cache_line_size = options.cacheline_size
>
> # If elastic trace generation is enabled, make sure the memory system
> is
> # minimal so that compute delays do not include memory access
> latencies.
> # Configure the compulsory L1 caches for the O3CPU, do not configure
> # any more caches.
> if options.l2cache and options.elastic_trace_en:
> fatal("When elastic trace is enabled, do not configure L2 caches.")
>
>
> if options.cpu_type == "arm_detailed":
> #try:
> #from O3_ARM_v7a import *
># except:
>  #   print "arm_detailed is unavailable. Did you compile the O3
> model?"
>   #  sys.exit(1)
>
> dcache_class, icache_class, l2_cache_class, l3_cache_class,
> v_cache_class, walk_cache_class = \
> O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2,
> O3_ARM_v7aL3, O3_ARM_v7aV, \
> O3_ARM_v7aWalkCache
> else:
> dcache_class, icache_class, l2_cache_class, l3_cache_class,
> v_cache_class, walk_cache_class = \
> L1_DCache, L1_ICache, L2Cache, L3Cache, VCache,