Hi Jaemin,
On 06.02.2018 16:23, Jaemin Park wrote:
> First of all, I really appreciate the comments that helped me a lot.
>
> Finally, I solved my problem.
...
> I hope this share can help others.
thank you very much for having taken the time to summarize your findings
for all of us! :-)
Cheers
Hi,
First of all, I really appreciate the comments that helped me a lot.
Finally, I solved my problem.
The most critical problem in my implementation was to use a virtual address
to make a Rom_module.
For the reference, I summarized my implementation as follows:
1) Core(repos/base/src/core/mai
Hi Jaemin,
On Tue, Feb 06, 2018 at 09:20:03AM +0900, Jaemin Park wrote:
> Hi,
>
> I'd like to add some log information for clarification.
>
> In Core, the address of populated rm_session(local_addr) is 0x12d000.
> When Rom_module is created inside Core, the address of it(rom_module) is
> also 0x
Hi,
I'd like to add some log information for clarification.
In Core, the address of populated rm_session(local_addr) is 0x12d000.
When Rom_module is created inside Core, the address of it(rom_module) is
also 0x12d000.
In tz_vmm, the address of local_data(attached to Dataspace_capability) is
0xc0
Hi,
I attempted to implement a read-only method to share a variable of Core.
My attempt showed me an error as follows:
Error: init -> tz_vmm -> ep: raised unhandled data abort DFSR=0x1008
ISFR=0x7 DFAR=0xc000 ip=0x70010c40 sp=0xe02fef00
My implementation is as follows(blue-colored parts):
1) C
Hi,
I really appreciate your kind and quick response.
In my case, a one-way read-only fashion is enough.
I'd like to share an information that other components can read only.
If you can give me an example or any reference code published in the git
repository, please let me know.
Sorry for a new
Hi Jaemin,
On Fri, Feb 02, 2018 at 11:28:53AM +0900, Jaemin Park wrote:
> Hi,
>
> I'd like to ask a question about a way to "share a variable of Core with
> other components".
>
> I'm using i.MX53 QSB, so this question is based on 'base-hw' implementation.
>
> Suppose that 'Core' has a variable