Hi,
I ran into a case which is Okay for Libero SoC but not Okay for GHDL.
I have the following component:
component RWRAM is
-- Delays are for nicer GHDL - gtkwave simulation
generic (
AssDelay : time := AssDelay;
RegDelay : time := RegDelay
I think the easiest „trick“ is to use an intermediate signal with 9 bits to
connect to oData
and then use only the 8 lower bits of it for HRDATA. That „problem is a very
common one, you
will see the same solution in many generated code which uses FPGA internal
components with
fixed port widths
On 12/01/15 20:56, Torsten Meissner wrote:
I think the easiest „trick“ is to use an intermediate signal with 9 bits to
connect to oData
and then use only the 8 lower bits of it for HRDATA. That „problem is a very
common one, you
will see the same solution in many generated code which uses FPGA
Am 12.01.2015 um 21:37 schrieb Tristan Gingold tging...@free.fr:
On 12/01/15 20:56, Torsten Meissner wrote:
I think the easiest „trick“ is to use an intermediate signal with 9 bits to
connect to oData
and then use only the 8 lower bits of it for HRDATA. That „problem is a
very common
Hello,
because I’m visiting the FOSDEM conference this year; I’ve looked through the
schedule.
Nice, there is a EDA and a ADA room. And the GHDL project is presented by
Tristan in the EDA room:
https://fosdem.org/2015/schedule/event/ghdl/
@Tristan:
Is there any short schedule of the talk, I
On 13/01/2015, at 9:37 am, Tristan Gingold tging...@free.fr wrote:
Indeed, GHDL is correct. See LRM93 4.3.2.2 Association lists:
Furthermore, every scalar subelement of the explicitly declared interface
object must be associated exactly once with an actual (or subelement thereof)
in the
