I had gone through and characterized your design looking for anomalies, also
looked at the previous one you had reported and Tristan responded to about
ghdl's slow-ish concatenation. The idea was to look for things before the
effort of profiling.
I found those 5,204 input vectors (bytes) that
On Tue, 2016-03-15 at 00:40 +0100, Adrien Prost-Boucle wrote:
> Hi,
>
> I had another idea.
>
> Re-evaluating the entire mux expressions is a heavy task.
> So would it be possible to re-evaluate only the sub-expressions that
> have changed? Including, for function calls, only those that have no
On 09/03/16 21:37, Adrien Prost-Boucle wrote:
Hi,
I have a VHDL design that GHDL simulates at a speed of only one or 2
clock cycles per second. The same design, same VHDL files, is simulated
by Xilinx Vivado 2015.3 at a speed of 400 clock cycles per second.
For all other designs I have and/or
