On 13/01/15 14:22, why...@f-cpu.org wrote:
Hello,
Le 2015-01-12 20:46, Endre Bak a écrit :
The tricky line is:
oData(7 downto 0) = HRDATA(8 * i + 7 downto 8 * i),
GHDL reports the following error:
AHBSlaveRAM.vhdl:78:29: no choice for 8
(Microsemi Libero SoC can synthesize it, just gives
Le 2015-01-13 20:32, Tristan Gingold a écrit :
On 13/01/15 14:22, why...@f-cpu.org wrote:
One thing I have not seen mentioned (or maybe my emails lag ?) is to
use
OPEN :
oData(8) = open,
Does that work in that case ?
No, not allowed by the LRM.
ah, i see why, OPEN works on a whole
Hello,
Le 2015-01-12 20:46, Endre Bak a écrit :
The tricky line is:
oData(7 downto 0) = HRDATA(8 * i + 7 downto 8 * i),
GHDL reports the following error:
AHBSlaveRAM.vhdl:78:29: no choice for 8
(Microsemi Libero SoC can synthesize it, just gives this message: @N:
CD367
Thanks! The dummy signal is good for both tools.
On Mon, Jan 12, 2015 at 11:24 PM, David Koontz diogra...@gmail.com wrote:
On 13/01/2015, at 9:37 am, Tristan Gingold tging...@free.fr wrote:
Indeed, GHDL is correct. See LRM93 4.3.2.2 Association lists:
Furthermore, every scalar
Hi,
I ran into a case which is Okay for Libero SoC but not Okay for GHDL.
I have the following component:
component RWRAM is
-- Delays are for nicer GHDL - gtkwave simulation
generic (
AssDelay : time := AssDelay;
RegDelay : time := RegDelay
I think the easiest „trick“ is to use an intermediate signal with 9 bits to
connect to oData
and then use only the 8 lower bits of it for HRDATA. That „problem is a very
common one, you
will see the same solution in many generated code which uses FPGA internal
components with
fixed port widths
On 12/01/15 20:56, Torsten Meissner wrote:
I think the easiest „trick“ is to use an intermediate signal with 9 bits to
connect to oData
and then use only the 8 lower bits of it for HRDATA. That „problem is a very
common one, you
will see the same solution in many generated code which uses FPGA
Am 12.01.2015 um 21:37 schrieb Tristan Gingold tging...@free.fr:
On 12/01/15 20:56, Torsten Meissner wrote:
I think the easiest „trick“ is to use an intermediate signal with 9 bits to
connect to oData
and then use only the 8 lower bits of it for HRDATA. That „problem is a
very common
On 13/01/2015, at 9:37 am, Tristan Gingold tging...@free.fr wrote:
Indeed, GHDL is correct. See LRM93 4.3.2.2 Association lists:
Furthermore, every scalar subelement of the explicitly declared interface
object must be associated exactly once with an actual (or subelement thereof)
in the
