Re: [Ghdl-discuss] Compile error: actual expression must be globally static

[David Koontz]

> On Nov 12, 2016, at 9:58 AM, Carlos Alberto Ruiz  > wrote:
>  
> Hello Andrey,
>  
> I've changed the code and made it compatible with standard VHDL.
>  
> ---

Non-static expressions as actuals in port map associations is a -2008 feature.

IEEE Std 1076-2008
6.5.6.3 Port clauses 
para 6:

If the actual part of a given association element for a formal port of a block 
is the reserved word inertial followed by an expression, or is an expression 
that is not globally static, then the given association element is equivalent 
to association of the port with an anonymous signal implicitly declared in the 
declarative region that immediately encloses the block. The signal has the same 
subtype as the formal port and is the target of an implicit concurrent signal 
assignment statement of the form

anonymous <= E;

where E is the expression in the actual part of the given association element. 
The concurrent signal assignment statement occurs in the same statement part as 
the block.

 --

The equivalent section in -2000 (-2002 or earlier) is 1.1.1.2 Ports, where 
paragraph 4 specifies an expression must be globally static:

To communicate with other blocks, the ports of a block can be associated with 
signals in the environment in which the block is used. Moreover, the ports of a 
block may be associated with an expression in order to provide these ports with 
constant driving values; such ports must be of mode in. A port is itself a 
signal (see 4.3.1.2); thus, a formal port of a block may be associated as an 
actual with a formal port of an inner block. The port, signal, or expression 
associated with a given formal port is called the actual corresponding to the 
formal port (see 4.3.2.2). The actual, if a port or signal, must be denoted by 
a static name (see 6.1). The actual, if an expression, must be a globally 
static expression (see 7.4).
 --

Also note that with the implicit signal you incur a simulation delta cycle 
delay in the assignment, something to take into account for zero delay modeling.

Also see Peter Ashenden and Jim Lewis's book 'VHDL 2008 Just the New Stuff' 
Chapter 6 Modeling Enhancements, 6.1 Signal Expressions in Port Maps.

I don't believe ghdl supports non-static expressions as actual with --std=08 
(as yet). 

I'd dispute it's any more succinct - although brief, not clearly expressed 
because of the hidden delta cycle delay in the implicitly declared signal 
assignment. 

> El 11-11-2016 15:34, Andrey Gursky escribió:
> 
>> Hi Carlos,
>> 
>> On Tue, 25 Oct 2016 16:39:51 +0200 Carlos Alberto Ruiz wrote:
>> 
>>> Thanks for the response Andrey Gursky. 
>>> 
>>> I use VHDL 2000. Im having errors in a lot of ports. For example: 
>>> 
>>>  signal in_0 : std_logic; 
>>>  signal out_0 : std_logic';
>>> 
>>>  signal out_1 : std_logic';
>>> 
>>>  IP0: ip0 port map (
>>>  input => in_0 & in_0, -- ERROR
>>>  output => out_0
>>>  );
>>> 
>>>  IP1: ip1 port map (
>>>  input => out_0 and out_0, -- ERROR
>>>  output => out_1
>>>  ); 
>>> 
>>> I can´t put expression in ports. Is there any way you could do it? I
>>> have a really big design and is very tedious change everything.
>>> I want to use GHDL with VUNIT, so I would not change compiler.
>> 

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Re: [Ghdl-discuss] Compile error: actual expression must be globally static

[Carlos Alberto Ruiz]

 

Hello Andrey, 

I've changed the code and made it compatible with standard VHDL. 

---

CARLOS ALBERTO RUIZ NARANJO
_FPGA engineer_
 cr...@dasphotonics.com 

__ 

DAS PHOTONICS S.L. 
Ciudad Politécnica de la Innovación, Camino de Vera s/n.
Acceso K, Edificio 8F, 2ª planta 46022 Valencia - SPAIN
Telf: +34 963 556 150 - Directo: +34 -- 

www.dasphotonics.com [3] 

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El 11-11-2016 15:34, Andrey Gursky escribió: 

> Hi Carlos,
> 
> On Tue, 25 Oct 2016 16:39:51 +0200 Carlos Alberto Ruiz wrote:
> 
>> Thanks for the response Andrey Gursky. 
>> 
>> I use VHDL 2000. Im having errors in a lot of ports. For example: 
>> 
>> signal in_0 : std_logic; 
>> signal out_0 : std_logic';
>> 
>> signal out_1 : std_logic';
>> 
>> IP0: ip0 port map (
>> input => in_0 & in_0, -- ERROR
>> output => out_0
>> );
>> 
>> IP1: ip1 port map (
>> input => out_0 and out_0, -- ERROR
>> output => out_1
>> ); 
>> 
>> I can´t put expression in ports. Is there any way you could do it? I
>> have a really big design and is very tedious change everything.
>> I want to use GHDL with VUNIT, so I would not change compiler.
> 
> In order to compile with GHDL I had to go and change the code. Could
> you avoid this?
> 
> Regards,
> Andrey
> On 25-10-2016 14:59, Andrey Gursky wrote: 
> 
> Hi,
> 
> On Tue, 25 Oct 2016 14:19:49 +0200
> Carlos Alberto Ruiz wrote:
> 
> Hello, 
> 
> I have this error to compile: 
> 
> /home/cruiz/ELINT/95512010_FPGA_central/src/tosca2/tosca2_ifc_suser_elint_agsw.vhd:2078:58:
> actual expression must be globally static 
> 
> In this line: 
> 
> port map(id_ch1 => i_fmc1(0,7) & i_fmc1(0,6) & i_fmc1(0,5) &
> i_fmc1(0,4)
> & i_fmc1(0,3) & i_fmc1(0,2) & i_fmc1(0,1) & i_fmc1(0,0), 
> 
> I have the same problem in Xilins, but its only a waring. 
> Are you sure, the expression is indeed globally static?
> 
> From my experience [1 [1]], Xilinx warns you about violating the VHDL
> standard (by the way, what version do you use?), though such standard's
> constraints are really artificial and have been overcome many years ago
> by proprietary vendors such as Xilinx and Altera, but unfortunately not
> GHDL. At least the issue I've encountered could be easy fixed in
> another VHDL simulator [2 [2]].
> 
> Regards,
> Andrey
> 
> [1 [1]] relax "choice must be locally static expression"
> https://sourceforge.net/p/ghdl-updates/tickets/40/ [1] [1 [1]]
> 
> [2 [2]] VHDL compiler and simulator
> https://github.com/nickg/nvc [2] [2 [2]]

Links:
--
[1] https://sourceforge.net/p/ghdl-updates/tickets/40/ [1]
[2] https://github.com/nickg/nvc [2] 

Links:
--
[1] https://sourceforge.net/p/ghdl-updates/tickets/40/
[2] https://github.com/nickg/nvc
[3] http://www.dasphotonics.com/
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Re: [Ghdl-discuss] Compile error: actual expression must be globally static

[Andrey Gursky]

Hi Carlos,

On Tue, 25 Oct 2016 16:39:51 +0200 Carlos Alberto Ruiz wrote:

> Thanks for the response Andrey Gursky. 
> 
> I use VHDL 2000. Im having errors in a lot of ports. For example: 
> 
>  signal in_0 : std_logic; 
>  signal out_0 : std_logic';
> 
>  signal out_1 : std_logic';
> 
>  IP0: ip0 port map (
>  input => in_0 & in_0, -- ERROR
>  output => out_0
>  );
> 
>  IP1: ip1 port map (
>  input => out_0 and out_0, -- ERROR
>  output => out_1
>  ); 
> 
> I can´t put expression in ports. Is there any way you could do it? I
> have a really big design and is very tedious change everything.
> I want to use GHDL with VUNIT, so I would not change compiler. 

In order to compile with GHDL I had to go and change the code. Could
you avoid this?

Regards,
Andrey
 
> On 25-10-2016 14:59, Andrey Gursky wrote: 
> 
> > Hi,
> > 
> > On Tue, 25 Oct 2016 14:19:49 +0200
> > Carlos Alberto Ruiz wrote:
> > 
> >> Hello, 
> >> 
> >> I have this error to compile: 
> >> 
> >> /home/cruiz/ELINT/95512010_FPGA_central/src/tosca2/tosca2_ifc_suser_elint_agsw.vhd:2078:58:
> >> actual expression must be globally static 
> >> 
> >> In this line: 
> >> 
> >> port map(id_ch1 => i_fmc1(0,7) & i_fmc1(0,6) & i_fmc1(0,5) &
> >> i_fmc1(0,4)
> >> & i_fmc1(0,3) & i_fmc1(0,2) & i_fmc1(0,1) & i_fmc1(0,0), 
> >> 
> >> I have the same problem in Xilins, but its only a waring.
> > 
> > Are you sure, the expression is indeed globally static?
> > 
> > From my experience [1], Xilinx warns you about violating the VHDL
> > standard (by the way, what version do you use?), though such standard's
> > constraints are really artificial and have been overcome many years ago
> > by proprietary vendors such as Xilinx and Altera, but unfortunately not
> > GHDL. At least the issue I've encountered could be easy fixed in
> > another VHDL simulator [2].
> > 
> > Regards,
> > Andrey
> > 
> > [1] relax "choice must be locally static expression"
> > https://sourceforge.net/p/ghdl-updates/tickets/40/ [1]
> > 
> > [2] VHDL compiler and simulator
> > https://github.com/nickg/nvc [2]
>  
> 
> Links:
> --
> [1] https://sourceforge.net/p/ghdl-updates/tickets/40/
> [2] https://github.com/nickg/nvc

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Re: [Ghdl-discuss] Compile error: actual expression must be globally static

[Brian L. Drummond]

Is this one of the rules affected by the -frelaxed-rules compile option?



From: Ghdl-discuss  on behalf of Carlos Alberto 
Ruiz 
Sent: 25 October 2016 15:39:51
To: Andrey Gursky
Cc: GHDL discuss list
Subject: Re: [Ghdl-discuss] Compile error: actual expression must be globally 
static




Thanks for the response Andrey Gursky.

I use VHDL 2000. Im having errors in a lot of ports. For example:

 signal in_0 : std_logic;
 signal out_0 : std_logic';
 signal out_1 : std_logic';

  IP0: ip0 port map (
  input => in_0 & in_0,  -- ERROR
  output => out_0
);

 IP1: ip1 port map (
  input => out_0 and out_0,  -- ERROR
  output => out_1
);

I can?t put expression in ports. Is there any way you could do it? I have a 
really big design and is very tedious change everything.

I want to use GHDL with VUNIT, so I would not change compiler.



Carlos Alberto Ruiz Naranjo
FPGA engineer
cr...@dasphotonics.com

[http://dasphotonics.com/images/logo.jpg]

DAS Photonics S.L.
Ciudad Polit?cnica de la Innovaci?n, Camino de Vera s/n.
Acceso K, Edificio 8F, 2? planta 46022 Valencia - SPAIN
Telf: +34 963 556 150 - Directo: +34 --

www.dasphotonics.com <http://www.dasphotonics.com/>

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This e-mail contains confidential information.It is for the intended recipient 
only. If you are not the intended recipient of this e-mail, please notify the 
author by replying to this e-mail immediately and delete the message from your 
computer. If you are not the intended recipient you must not use, disclose, 
distribute, copy, print or rely on this e-mail



On 25-10-2016 14:59, Andrey Gursky wrote:

Hi,

On Tue, 25 Oct 2016 14:19:49 +0200
Carlos Alberto Ruiz mailto:cr...@dasphotonics.com>> 
wrote:

Hello,

I have this error to compile:

/home/cruiz/ELINT/95512010_FPGA_central/src/tosca2/tosca2_ifc_suser_elint_agsw.vhd:2078:58:
actual expression must be globally static

In this line:

 port map(id_ch1 => i_fmc1(0,7) & i_fmc1(0,6) & i_fmc1(0,5) &
i_fmc1(0,4)
 & i_fmc1(0,3) & i_fmc1(0,2) & i_fmc1(0,1) & i_fmc1(0,0),

I have the same problem in Xilins, but its only a waring.

Are you sure, the expression is indeed globally static?

>From my experience [1], Xilinx warns you about violating the VHDL
standard (by the way, what version do you use?), though such standard's
constraints are really artificial and have been overcome many years ago
by proprietary vendors such as Xilinx and Altera, but unfortunately not
GHDL. At least the issue I've encountered could be easy fixed in
another VHDL simulator [2].

Regards,
Andrey

[1] relax "choice must be locally static expression"
https://sourceforge.net/p/ghdl-updates/tickets/40/

[2] VHDL compiler and simulator
https://github.com/nickg/nvc
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Re: [Ghdl-discuss] Compile error: actual expression must be globally static

[Carlos Alberto Ruiz]

 

Thanks for the response Andrey Gursky. 

I use VHDL 2000. Im having errors in a lot of ports. For example: 

 signal in_0 : std_logic; 
 signal out_0 : std_logic';

 signal out_1 : std_logic';

 IP0: ip0 port map (
 input => in_0 & in_0, -- ERROR
 output => out_0
 );

 IP1: ip1 port map (
 input => out_0 and out_0, -- ERROR
 output => out_1
 ); 

I can´t put expression in ports. Is there any way you could do it? I
have a really big design and is very tedious change everything.
I want to use GHDL with VUNIT, so I would not change compiler. 

CARLOS ALBERTO RUIZ NARANJO
_FPGA engineer_
 cr...@dasphotonics.com 

__ 

DAS PHOTONICS S.L. 
Ciudad Politécnica de la Innovación, Camino de Vera s/n.
Acceso K, Edificio 8F, 2ª planta 46022 Valencia - SPAIN
Telf: +34 963 556 150 - Directo: +34 -- 

www.dasphotonics.com [3] 

Before printing this email think well whether it is really necessary.
This e-mail contains confidential information.It is for the intended
recipient only. If you are not the intended recipient of this e-mail,
please notify the author by replying to this e-mail immediately and
delete the message from your computer. If you are not the intended
recipient you must not use, disclose, distribute, copy, print or rely on
this e-mail 

On 25-10-2016 14:59, Andrey Gursky wrote: 

> Hi,
> 
> On Tue, 25 Oct 2016 14:19:49 +0200
> Carlos Alberto Ruiz  wrote:
> 
>> Hello, 
>> 
>> I have this error to compile: 
>> 
>> /home/cruiz/ELINT/95512010_FPGA_central/src/tosca2/tosca2_ifc_suser_elint_agsw.vhd:2078:58:
>> actual expression must be globally static 
>> 
>> In this line: 
>> 
>> port map(id_ch1 => i_fmc1(0,7) & i_fmc1(0,6) & i_fmc1(0,5) &
>> i_fmc1(0,4)
>> & i_fmc1(0,3) & i_fmc1(0,2) & i_fmc1(0,1) & i_fmc1(0,0), 
>> 
>> I have the same problem in Xilins, but its only a waring.
> 
> Are you sure, the expression is indeed globally static?
> 
> From my experience [1], Xilinx warns you about violating the VHDL
> standard (by the way, what version do you use?), though such standard's
> constraints are really artificial and have been overcome many years ago
> by proprietary vendors such as Xilinx and Altera, but unfortunately not
> GHDL. At least the issue I've encountered could be easy fixed in
> another VHDL simulator [2].
> 
> Regards,
> Andrey
> 
> [1] relax "choice must be locally static expression"
> https://sourceforge.net/p/ghdl-updates/tickets/40/ [1]
> 
> [2] VHDL compiler and simulator
> https://github.com/nickg/nvc [2]
 

Links:
--
[1] https://sourceforge.net/p/ghdl-updates/tickets/40/
[2] https://github.com/nickg/nvc
[3] http://www.dasphotonics.com/
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Re: [Ghdl-discuss] Compile error: actual expression must be globally static

[Andrey Gursky]

Hi,

On Tue, 25 Oct 2016 14:19:49 +0200
Carlos Alberto Ruiz  wrote:

> Hello, 
> 
> I have this error to compile: 
> 
> /home/cruiz/ELINT/95512010_FPGA_central/src/tosca2/tosca2_ifc_suser_elint_agsw.vhd:2078:58:
> actual expression must be globally static 
> 
> In this line: 
> 
>  port map(id_ch1 => i_fmc1(0,7) & i_fmc1(0,6) & i_fmc1(0,5) &
> i_fmc1(0,4)
>  & i_fmc1(0,3) & i_fmc1(0,2) & i_fmc1(0,1) & i_fmc1(0,0), 
> 
> I have the same problem in Xilins, but its only a waring. 

Are you sure, the expression is indeed globally static?

From my experience [1], Xilinx warns you about violating the VHDL
standard (by the way, what version do you use?), though such standard's
constraints are really artificial and have been overcome many years ago
by proprietary vendors such as Xilinx and Altera, but unfortunately not
GHDL. At least the issue I've encountered could be easy fixed in
another VHDL simulator [2].

Regards,
Andrey

[1] relax "choice must be locally static expression"
https://sourceforge.net/p/ghdl-updates/tickets/40/

[2] VHDL compiler and simulator
https://github.com/nickg/nvc

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