Re: [Ghdl-discuss] Synthesis for FPGAs / XML dump

2016-11-14 Thread Martin Strubel

On 11/04/2016 01:34 PM, why...@f-cpu.org wrote:

Le 2016-11-04 10:59, Martin Strubel a écrit :

On the other side there's a lot of possibilities for fun stuff, like
creating SVG images from the XML using built-in browser XSL abilities.


That's the best-looking idea of today !
I want that :-)



Thy wish shall be heard.

Put up a Q demo. Just drag the output from --file-to-xml using your 
file manager onto the canvas. Tested with recent Firefox only:


http://section5.ch/dclib/xhdl/

And in case: no worries, as noted, none of your design data is 
transmitted anywhere.


Cheers,

- Strubi


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Re: [Ghdl-discuss] Synthesis for FPGAs / XML dump

2016-10-24 Thread Martin Strubel

Hi Tristan,

thanks for the snippet. Played around a bit with XSL and got some usable 
output just for dumping purposes. Reality will be far more complex though...



4) I was wondering, if it was actually possible to hack an .XSL to
extract register assignments as the above, or if a more complex tree
parsing via a "real" programming language was required.


I fear that xsl is not the best way to write a syntheziser...



I'd tend to say "impossible", but in in a few cases so far I found ways 
to translate from XML dialect A into dialect B which again can be 
processed easier, without going through complex classical DOM parsing 
solutions (saxon/expat/...).
So a possible first step could be to identify constructs that synthesize 
and express them in an easier-to read (and *then* schematize via XSD) 
XML language.
I've played around in the past with the Python/MyHDL approach (with the 
built-in native access to the AST) to generate RTL for DSP units. Not 
considered "nice", but usable. Nice would be to have an intermediate 
"XML DNA", but that's way more complex than a few DSP slices...


I also liked YG's idea/approach with the virtual machine, but the path 
from a 'simulation primitive' (event driven logic) to a level where the 
VM would know how to handle a HDL-Design with a set of FPGA technology 
elements seems already more complex than a HDL analysis based on the 
actual code (via AST) with a mapping stage in between. Wild dreaming: 
Deploy machine learning algos (but spend a few years on research...)


But the coverage aspect of it is very nice, also, a different way of 
optimization could take place, that considers the real application 
scenario based on the test bench. It might also give a lot more control 
to place & route from a mapper level. Can't think of the time burnt just 
because tools do what they want by just crunching brute force in the 
wrong direction. And then it's a bad time having to reverse engineer and 
find out: The human brain is often the better router.


Cheers,

- Martin



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Re: [Ghdl-discuss] Synthesis for FPGAs / XML dump

2016-10-17 Thread whygee

Le 2016-10-17 20:59, Tristan Gingold a écrit :

On 17/10/16 12:54, why...@f-cpu.org wrote:

I didn't know it would be so easy,
however I am wondering : the AST describes the
circuit but what about the elaboration ?

The XML represents the VHDL file after analysis.

Then I suppose that the synthesiser
must perform elaboration...


Tristan.

yg

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Re: [Ghdl-discuss] Synthesis for FPGAs / XML dump

2016-10-17 Thread Tristan Gingold

On 17/10/16 12:54, why...@f-cpu.org wrote:

Le 2016-10-17 12:37, Salvador Eduardo Tropea a écrit :

El 15/10/16 a las 03:21, Tristan Gingold escribió:

I have just added a new command to dump the AST tree in XML:
ghdl --file-to-xml FILEs

Thanks!


Thanks from me too !

I didn't know it would be so easy,
however I am wondering : the AST describes the
circuit but what about the elaboration ?


The XML represents the VHDL file after analysis.

Tristan.


My idea of running a virtual machine of a tagged
architecture would solve this because the elaboration
would elaborate properly...
What detail did I miss ?


Regards, Salvador

yg

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Re: [Ghdl-discuss] Synthesis for FPGAs / XML dump

2016-10-17 Thread Tristan Gingold

On 17/10/16 11:29, Martin Strubel wrote:


Hi Tristan,



Comments and suggestions are welcome.


1) Cool stuff! That might come in very handy for Co-Simulation and other
code analysis
2) Could you post a simple example XML output of a FF/register
assignment (only if you have the nerve for it, of course), e.g.

process(clk)
begin
if rising_edge(clk) then
if en = '1' then
r0 <= r1;
end if;
end if;
end process;


The interesting part of the xml is:

  
file="ex.vhdl"

 line="12" col="3" label="" seen_flag="false"
 end_has_postponed="false" passive_flag="false"
 postponed_flag="false" visible_flag="false"
 is_within_flag="false" has_label="false" has_is="false"
 end_has_reserved_id="true" end_has_identifier="false"
 wait_state="unknown">
  
  
line="14"
 col="5" label="" suspend_flag="false" 
visible_flag="false"

 end_has_identifier="false">
  
  file="ex.vhdl"

   line="14" col="8" expr_staticness="none"
   name_staticness="none">

  
  
  



  kind="association_element_by_expression"

   file="ex.vhdl" line="14" col="20"
   whole_association_flag="true"
   collapse_signal_flag="false">
file="ex.vhdl"

 line="14" col="20" identifier="clk"
 is_forward_ref="false" expr_staticness="none"
 name_staticness="local">
  
  
  

  



  
  

  
  

file="ex.vhdl"

 line="15" col="8" identifier="en"
 is_forward_ref="false" expr_staticness="none"
 name_staticness="local">
  
  
  


 file="ex.vhdl" line="15" col="13" 
identifier="'1'"

 is_forward_ref="false" expr_staticness="local"
 name_staticness="local">
  
  
  

  
  
 delay_mechanism="inertial" 
visible_flag="false"

 guarded_target_state="false">
  
 expr_staticness="none" 
name_staticness="local">




  
  

  



  

  

  

  

  
  
line="12"

 col="11" identifier="clk" is_forward_ref="false"
 expr_staticness="none" name_staticness="local">
  
  
  

  

  


3) Someone mentioned a schema (XSD), this sounds like an awful lot of
work to me, esp. at an early stage, when things might change. I'd rather
see many conversion examples.


I have never written XSD, to I cannot really comment.


4) I was wondering, if it was actually possible to hack an .XSL to
extract register assignments as the above, or if a more complex tree
parsing via a "real" programming language was required.


I fear that xsl is not the best way to write a syntheziser...

Tristan.


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Re: [Ghdl-discuss] Synthesis for FPGAs / XML dump

2016-10-17 Thread whygee

Le 2016-10-17 12:37, Salvador Eduardo Tropea a écrit :

El 15/10/16 a las 03:21, Tristan Gingold escribió:

I have just added a new command to dump the AST tree in XML:
ghdl --file-to-xml FILEs

Thanks!


Thanks from me too !

I didn't know it would be so easy,
however I am wondering : the AST describes the
circuit but what about the elaboration ?
My idea of running a virtual machine of a tagged
architecture would solve this because the elaboration
would elaborate properly...
What detail did I miss ?


Regards, Salvador

yg

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Re: [Ghdl-discuss] Synthesis for FPGAs / XML dump

2016-10-17 Thread Salvador Eduardo Tropea

El 15/10/16 a las 03:21, Tristan Gingold escribió:

I have just added a new command to dump the AST tree in XML:
ghdl --file-to-xml FILEs


Thanks!

Regards, Salvador

--
Ing. Salvador Eduardo Tropea  http://utic.inti.gob.ar/
INTI - Micro y Nanoelectrónica (CMNB) http://www.inti.gob.ar/
Unidad Técnica Sistemas Inteligentes  Av. General Paz 5445
Tel: (+54 11) 4724 6300 ext. 6919 San Martín - B1650KNA
FAX: (+54 11) 4754 5194   Buenos Aires * Argentina





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Re: [Ghdl-discuss] Synthesis for FPGAs / XML dump

2016-10-15 Thread Patrick Lehmann
Regarding "we":My viewer somehow introduced a linebreak and created a standalone we tag :)Mistery solved.---Wissenschaftliche HilfskraftTechnische Universität DresdenFakultät InformatikInstitut für Technische InformatikLehrstuhl VLSI-Entwurfssysteme, Diagnostik und Architektur 01062 Dresden, GERMANYTel.:  +49 351 463-38451   Fax:  +49 351 463-38324E-Mail: patrick.lehm...@tu-dresden.de   WWW:http://vlsi-eda.inf.tu-dresden.de Ursprüngliche Nachricht Von: Tristan Gingold <tging...@free.fr> Datum:15.10.2016  11:49  (GMT+01:00) An: ghdl-discuss@gna.org Betreff: Re: [Ghdl-discuss] Synthesis for FPGAs / XML dump 
On 15/10/16 11:07, Patrick Lehmann wrote:
> Hello Tristan,
>
> I have seen many bad structured XML formats in my life, but GHDL's
> output looks VERY GOOD! Especially that you use XML attributes and ids.

It is written by hand and not very complex.
Nodes have id, lists have list-id.  This is not very regular, so maybe 
all XML elements must have id (I will certainly use nXX for nodes and 
lXX for lists in that case).

> Two notes:
> 1)
> You are almost using long readable names except for el and we. Can give
> the long name?

el stands for element of a list or of a chain.  That's not very 
interesting so I plan to keep it.

we ?  No, it doesn't exist.  There is we_value which stands for 
waveform_element_value.  This comes directly from iirs.ads, so no plan 
to change it immediately.

> 2)
> The output needs a root element like design_file and a version number
> for the AST version.

That was only an excerpt.  The start of the file is:



   
    identifier="std" date="12"
...

Adding a version to root is a good idea.

Tristan.


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Re: [Ghdl-discuss] Synthesis for FPGAs / XML dump

2016-10-15 Thread Tristan Gingold

On 15/10/16 11:07, Patrick Lehmann wrote:

Hello Tristan,

I have seen many bad structured XML formats in my life, but GHDL's
output looks VERY GOOD! Especially that you use XML attributes and ids.


It is written by hand and not very complex.
Nodes have id, lists have list-id.  This is not very regular, so maybe 
all XML elements must have id (I will certainly use nXX for nodes and 
lXX for lists in that case).



Two notes:
1)
You are almost using long readable names except for el and we. Can give
the long name?


el stands for element of a list or of a chain.  That's not very 
interesting so I plan to keep it.


we ?  No, it doesn't exist.  There is we_value which stands for 
waveform_element_value.  This comes directly from iirs.ads, so no plan 
to change it immediately.



2)
The output needs a root element like design_file and a version number
for the AST version.


That was only an excerpt.  The start of the file is:



  https://mail.gna.org/listinfo/ghdl-discuss


Re: [Ghdl-discuss] Synthesis for FPGAs / XML dump

2016-10-15 Thread Patrick Lehmann
Hello Tristan,I have seen many bad structured XML formats in my life, but GHDL's output looks VERY GOOD! Especially that you use XML attributes and ids.Two notes:1)You are almost using long readable names except for el and we. Can give the long name?2)The output needs a root element like design_file and a version number for the AST version.To the community: Is an XSD required?E.g. It allows easier versioning and better tool integrations.Kind regards   Patrick ---Wissenschaftliche HilfskraftTechnische Universität DresdenFakultät InformatikInstitut für Technische InformatikLehrstuhl VLSI-Entwurfssysteme, Diagnostik und Architektur 01062 Dresden, GERMANYTel.:  +49 351 463-38451   Fax:  +49 351 463-38324E-Mail: patrick.lehm...@tu-dresden.de   WWW:http://vlsi-eda.inf.tu-dresden.de Ursprüngliche Nachricht Von: Tristan Gingold <tging...@free.fr> Datum:15.10.2016  08:22  (GMT+01:00) An: ghdl-discuss@gna.org Betreff: Re: [Ghdl-discuss] Synthesis for FPGAs / XML dump 
Hello,

I have just added a new command to dump the AST tree in XML:
ghdl --file-to-xml FILEs

The output can be very large (XML is not compact, and even std.standard 
is not small).  See iirs.ads for documentation of the fields.

Enjoy (or not).

Comments and suggestions are welcome.

Tristan.

As an example, the XML part for:

architecture behav of simple1 is
   signal s : bit;
begin
   s <= '1';

   process
   begin
 report "Start of simple1" severity note;
 assert s = '0' severity failure;
 wait for 0 ns;
 assert s = '1' severity failure;
 wait;
   end process;
end behav;


is:

 
file="simple1.vhdl"
  line="4" col="14" identifier="behav" foreign_flag="false"
  visible_flag="true" is_within_flag="false"
  end_has_reserved_id="false" end_has_identifier="true">
   
   
    line="4" col="23" identifier="simple1" 
is_forward_ref="false"
    expr_staticness="???" name_staticness="???">
 
   
   
 
  line="5" col="10" identifier="s" 
has_disconnect_flag="false"
  has_active_flag="false" has_identifier_list="false"
  visible_flag="true" after_drivers_flag="false"
  use_flag="false" is_ref="false" 
guarded_signal_flag="false"
  signal_kind="bus" expr_staticness="none"
  name_staticness="local">
   
   
    file="simple1.vhdl" line="5" col="14" identifier="bit"
    is_forward_ref="false" expr_staticness="???"
    name_staticness="???">
 
 
 
   
   
 
   
   
 
  file="simple1.vhdl" line="7" col="3" label=""
  delay_mechanism="inertial" postponed_flag="false"
  visible_flag="false" guarded_target_state="false">
   
   
    line="7" col="3" identifier="s" is_forward_ref="false"
    expr_staticness="none" name_staticness="local">
 
 
 
   
   
 
file="simple1.vhdl"
  line="7" col="8">
   
    file="simple1.vhdl" line="7" col="8" 
identifier="'1'"
    is_forward_ref="false" expr_staticness="local"
    name_staticness="local">
 
 
 
   
 
   
 
 
  line="9" col="3" label="" seen_flag="false"
  end_has_postponed="false" suspend_flag="true"
  passive_flag="false" postponed_flag="false"
  visible_flag="false" is_within_fla

Re: [Ghdl-discuss] Synthesis for FPGAs / XML dump

2016-10-15 Thread Tristan Gingold

Hello,

I have just added a new command to dump the AST tree in XML:
ghdl --file-to-xml FILEs

The output can be very large (XML is not compact, and even std.standard 
is not small).  See iirs.ads for documentation of the fields.


Enjoy (or not).

Comments and suggestions are welcome.

Tristan.

As an example, the XML part for:

architecture behav of simple1 is
  signal s : bit;
begin
  s <= '1';

  process
  begin
report "Start of simple1" severity note;
assert s = '0' severity failure;
wait for 0 ns;
assert s = '1' severity failure;
wait;
  end process;
end behav;


is:

file="simple1.vhdl"

 line="4" col="14" identifier="behav" foreign_flag="false"
 visible_flag="true" is_within_flag="false"
 end_has_reserved_id="false" end_has_identifier="true">
  
 line="4" col="23" identifier="simple1" 
is_forward_ref="false"

   expr_staticness="???" name_staticness="???">

  
  
 line="5" col="10" identifier="s" 
has_disconnect_flag="false"

 has_active_flag="false" has_identifier_list="false"
 visible_flag="true" after_drivers_flag="false"
 use_flag="false" is_ref="false" 
guarded_signal_flag="false"

 signal_kind="bus" expr_staticness="none"
 name_staticness="local">
  
  



  
  

  
  

  
  



  
  
file="simple1.vhdl"

 line="7" col="8">
 file="simple1.vhdl" line="7" col="8" 
identifier="'1'"

   is_forward_ref="false" expr_staticness="local"
   name_staticness="local">



  

  

 visible_flag="false" is_within_flag="false" 
has_label="false"

 has_is="false" end_has_reserved_id="true"
 end_has_identifier="false" wait_state="unknown">
  
  
file="simple1.vhdl"

 line="11" col="5" label="" visible_flag="false">
  
 file="simple1.vhdl" line="11" col="40" 
identifier="note"

   is_forward_ref="false" expr_staticness="local"
   name_staticness="local">



  
 string_length="16" has_signed="false" 
has_sign="false"

   has_length="false" bit_string_base="BASE_NONE"
   expr_staticness="local">


 kind="array_subtype_definition" 
file="simple1.vhdl"

 line="11" col="12" resolved_flag="false"
 signal_type_flag="true" has_signal_flag="false"
 index_constraint_flag="true" 
type_staticness="local"

 constraint_state="fully constrained">
  

  

  




  
  

  
  
  
  


  

file="simple1.vhdl"

 line="12" col="5" label="" visible_flag="false">
  
  kind="equality_operator"

   file="simple1.vhdl" line="12" col="14"
   expr_staticness="none">

file="simple1.vhdl"

 line="12" col="12" identifier="s"
 is_forward_ref="false" expr_staticness="none"
 name_staticness="local">