Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=20474abda6bb11396434593daf2f52679cf62edf
Commit: 20474abda6bb11396434593daf2f52679cf62edf
Parent: fb293ae1c02dab78e714d50f2c37d7852d6f328a
Author: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
AuthorDate: Sun Oct 28 08:49:28 2007 +1100
Committer: Paul Mackerras <[EMAIL PROTECTED]>
CommitDate: Thu Nov 8 14:15:30 2007 +1100
[POWERPC] Fix cache line vs. block size confusion
We had an historical confusion in the kernel between cache line
and cache block size. The former is an implementation detail of
the L1 cache which can be useful for performance optimisations,
the later is the actual size on which the cache control
instructions operate, which can be different.
For some reason, we had a weird hack reading the right property
on powermac and the wrong one on any other 64 bits (32 bits is
unaffected as it only uses the cputable for cache block size
infos at this stage).
This fixes the booting-without-of.txt documentation to mention
the right properties, and fixes the 64 bits initialization code
to look for the block size first, with a fallback to the line
size if the property is missing.
Signed-off-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
Signed-off-by: Paul Mackerras <[EMAIL PROTECTED]>
---
Documentation/powerpc/booting-without-of.txt | 14 ++++++++++++--
arch/powerpc/kernel/setup_64.c | 19 +++++++------------
2 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/Documentation/powerpc/booting-without-of.txt
b/Documentation/powerpc/booting-without-of.txt
index a96e853..2233e3d 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -851,12 +851,18 @@ address which can extend beyond that limit.
/cpus/PowerPC,[EMAIL PROTECTED]
/cpus/PowerPC,[EMAIL PROTECTED]
(unit addresses do not require leading zeroes)
- - d-cache-line-size : one cell, L1 data cache line size in bytes
- - i-cache-line-size : one cell, L1 instruction cache line size in
+ - d-cache-block-size : one cell, L1 data cache block size in bytes (*)
+ - i-cache-block-size : one cell, L1 instruction cache block size in
bytes
- d-cache-size : one cell, size of L1 data cache in bytes
- i-cache-size : one cell, size of L1 instruction cache in bytes
+(*) The cache "block" size is the size on which the cache management
+instructions operate. Historically, this document used the cache
+"line" size here which is incorrect. The kernel will prefer the cache
+block size and will fallback to cache line size for backward
+compatibility.
+
Recommended properties:
- timebase-frequency : a cell indicating the frequency of the
@@ -870,6 +876,10 @@ address which can extend beyond that limit.
for the above, the common code doesn't use that property, but
you are welcome to re-use the pSeries or Maple one. A future
kernel version might provide a common function for this.
+ - d-cache-line-size : one cell, L1 data cache line size in bytes
+ if different from the block size
+ - i-cache-line-size : one cell, L1 instruction cache line size in
+ bytes if different from the block size
You are welcome to add any property you find relevant to your board,
like some information about the mechanism used to soft-reset the
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index ede77db..3b1529c 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -291,23 +291,16 @@ static void __init initialize_cache_info(void)
if ( num_cpus == 1 ) {
const u32 *sizep, *lsizep;
u32 size, lsize;
- const char *dc, *ic;
-
- /* Then read cache informations */
- if (machine_is(powermac)) {
- dc = "d-cache-block-size";
- ic = "i-cache-block-size";
- } else {
- dc = "d-cache-line-size";
- ic = "i-cache-line-size";
- }
size = 0;
lsize = cur_cpu_spec->dcache_bsize;
sizep = of_get_property(np, "d-cache-size", NULL);
if (sizep != NULL)
size = *sizep;
- lsizep = of_get_property(np, dc, NULL);
+ lsizep = of_get_property(np, "d-cache-block-size",
NULL);
+ /* fallback if block size missing */
+ if (lsizep == NULL)
+ lsizep = of_get_property(np,
"d-cache-line-size", NULL);
if (lsizep != NULL)
lsize = *lsizep;
if (sizep == 0 || lsizep == 0)
@@ -324,7 +317,9 @@ static void __init initialize_cache_info(void)
sizep = of_get_property(np, "i-cache-size", NULL);
if (sizep != NULL)
size = *sizep;
- lsizep = of_get_property(np, ic, NULL);
+ lsizep = of_get_property(np, "i-cache-block-size",
NULL);
+ if (lsizep == NULL)
+ lsizep = of_get_property(np,
"i-cache-line-size", NULL);
if (lsizep != NULL)
lsize = *lsizep;
if (sizep == 0 || lsizep == 0)
-
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