Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=b773bb2e702f6ac96223018d621ea9ed0d4f23ff
Commit: b773bb2e702f6ac96223018d621ea9ed0d4f23ff
Parent: 19e75ea72b21136805218a2f55177e99100d62e5
Author: Matt Reimer <[EMAIL PROTECTED]>
AuthorDate: Thu Oct 18 17:43:07 2007 -0700
Committer: David Woodhouse <[EMAIL PROTECTED]>
CommitDate: Sat Oct 20 14:54:26 2007 +0100
[MTD] [NAND] add s3c2440-specific read_buf/write_buf
Add read_buf/write_buf for s3c2440, which can read/write 32 bits at a
time rather than just 8. In my testing on an s3c2440a running at 400 MHz
with a 100 MHz HCLK, read performance improves by 36% (from 5.19 MB/s
to 7.07 MB/s).
Signed-off-by: Matt Reimer <[EMAIL PROTECTED]>
Acked-by: Ben Dooks <[EMAIL PROTECTED]>
Signed-off-by: David Woodhouse <[EMAIL PROTECTED]>
---
drivers/mtd/nand/s3c2410.c | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
index 21b921d..66f76e9 100644
--- a/drivers/mtd/nand/s3c2410.c
+++ b/drivers/mtd/nand/s3c2410.c
@@ -488,12 +488,24 @@ static void s3c2410_nand_read_buf(struct mtd_info *mtd,
u_char *buf, int len)
readsb(this->IO_ADDR_R, buf, len);
}
+static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
+ readsl(info->regs + S3C2440_NFDATA, buf, len / 4);
+}
+
static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
int len)
{
struct nand_chip *this = mtd->priv;
writesb(this->IO_ADDR_W, buf, len);
}
+static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
int len)
+{
+ struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
+ writesl(info->regs + S3C2440_NFDATA, buf, len / 4);
+}
+
/* device management functions */
static int s3c2410_nand_remove(struct platform_device *pdev)
@@ -604,6 +616,8 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info
*info,
info->sel_bit = S3C2440_NFCONT_nFCE;
chip->cmd_ctrl = s3c2440_nand_hwcontrol;
chip->dev_ready = s3c2440_nand_devready;
+ chip->read_buf = s3c2440_nand_read_buf;
+ chip->write_buf = s3c2440_nand_write_buf;
break;
case TYPE_S3C2412:
-
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