Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=5a2c675c891960f86c025d4ab3d3904364bf4f96
Commit: 5a2c675c891960f86c025d4ab3d3904364bf4f96
Parent: 522a94bd1e18a2acf9428f48db585a2fc816559e
Author: Tim Small [EMAIL PROTECTED]
AuthorDate: Thu Jul 19 01:49:42 2007 -0700
Committer: Linus Torvalds [EMAIL PROTECTED]
CommitDate: Thu Jul 19 10:04:53 2007 -0700
drivers/edac: new i82443bxgz MC driver
This is a NEW EDAC Memory Controller driver for the 440BX chipset
(I82443BXGX)
created and submitted by Timm Small
Signed-off-by: Tim Small [EMAIL PROTECTED]
Signed-off-by: Douglas Thompson [EMAIL PROTECTED]
Signed-off-by: Andrew Morton [EMAIL PROTECTED]
Signed-off-by: Linus Torvalds [EMAIL PROTECTED]
---
drivers/edac/Kconfig |7 +
drivers/edac/Makefile |1 +
drivers/edac/i82443bxgx_edac.c | 400
3 files changed, 408 insertions(+), 0 deletions(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 772a290..b56e478 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -73,6 +73,13 @@ config EDAC_E752X
Support for error detection and correction on the Intel
E7520, E7525, E7320 server chipsets.
+config EDAC_I82443BXGX
+ tristate Intel 82443BX/GX (440BX/GX)
+ depends on EDAC_MM_EDAC PCI X86_32
+ help
+ Support for error detection and correction on the Intel
+ 82443BX/GX memory controllers (440BX/GX chipsets).
+
config EDAC_I82875P
tristate Intel 82875p (D82875P, E7210)
depends on EDAC_MM_EDAC PCI X86_32
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index d2674fb..773472c 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_EDAC_AMD76X) += amd76x_edac.o
obj-$(CONFIG_EDAC_I5000) += i5000_edac.o
obj-$(CONFIG_EDAC_E7XXX) += e7xxx_edac.o
obj-$(CONFIG_EDAC_E752X) += e752x_edac.o
+obj-$(CONFIG_EDAC_I82443BXGX) += i82443bxgx_edac.o
obj-$(CONFIG_EDAC_I82875P) += i82875p_edac.o
obj-$(CONFIG_EDAC_I82860) += i82860_edac.o
obj-$(CONFIG_EDAC_R82600) += r82600_edac.o
diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c
new file mode 100644
index 000..ecf2ba8
--- /dev/null
+++ b/drivers/edac/i82443bxgx_edac.c
@@ -0,0 +1,400 @@
+/*
+ * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
+ * module (C) 2006 Tim Small
+ *
+ * This file may be distributed under the terms of the GNU General
+ * Public License.
+ *
+ * Written by Tim Small [EMAIL PROTECTED], based on work by Linux
+ * Networx, Thayne Harbaugh, Dan Hollis goemon at anime dot net and
+ * others.
+ *
+ * 440GX fix by Jason Uhlenkott [EMAIL PROTECTED].
+ *
+ * Written with reference to 82443BX Host Bridge Datasheet:
+ * http://www.intel.com/design/chipsets/440/documentation.htm
+ * references to this document given in [].
+ *
+ * This module doesn't support the 440LX, but it may be possible to
+ * make it do so (the 440LX's register definitions are different, but
+ * not completely so - I haven't studied them in enough detail to know
+ * how easy this would be).
+ */
+
+#include linux/module.h
+#include linux/init.h
+
+#include linux/pci.h
+#include linux/pci_ids.h
+
+#include linux/slab.h
+
+#include edac_mc.h
+
+#define I82443_REVISION0.1
+
+#define EDAC_MOD_STRi82443bxgx_edac
+
+
+/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), Memory
+ * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
+ * rows The 82443BX supports multiple-bit error detection and
+ * single-bit error correction when ECC mode is enabled and
+ * single/multi-bit error detection when correction is disabled.
+ * During writes to the DRAM, the 82443BX generates ECC for the data
+ * on a QWord basis. Partial QWord writes require a read-modify-write
+ * cycle when ECC is enabled.
+*/
+
+/* Additionally, the 82443BX ensures that the data is corrected in
+ * main memory so that accumulation of errors is prevented. Another
+ * error within the same QWord would result in a double-bit error
+ * which is unrecoverable. This is known as hardware scrubbing since
+ * it requires no software intervention to correct the data in memory.
+ */
+
+/* [Also see page 100 (section 4.3), DRAM Interface]
+ * [Also see page 112 (section 4.6.1.4), ECC]
+ */
+
+#define I82443BXGX_NR_CSROWS 8
+#define I82443BXGX_NR_CHANS 1
+#define I82443BXGX_NR_DIMMS 4
+
+
+
+/* 82443 PCI Device 0 */
+#define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
+ * config space offset */
+#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
+ * row is non-ECC */
+#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz
