Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=108d093fdd75643dfc8c327f38125f4da76771e7
Commit: 108d093fdd75643dfc8c327f38125f4da76771e7
Parent: 32f3f49910c7e228839c1cd144dbed8da342703b
Author: Liam Girdwood <[EMAIL PROTECTED]>
AuthorDate: Thu Feb 8 16:23:29 2007 +0100
Committer: Russell King <[EMAIL PROTECTED]>
CommitDate: Thu Feb 8 15:27:15 2007 +0000
[ARM] 4152/1: Add PXA SSP audio register defs and fixups
This patchs adds some missing register bit defs for the PXA SSP ports audio
registers and fixes up some other broken bit definitions as noticed by Russell.
Signed-off-by: Liam Girdwood <[EMAIL PROTECTED]>
Signed-off-by: Russell King <[EMAIL PROTECTED]>
---
include/asm-arm/arch-pxa/pxa-regs.h | 19 +++++++++++--------
1 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h
b/include/asm-arm/arch-pxa/pxa-regs.h
index e24f6b6..20576d1 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -474,8 +474,8 @@
#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX
and RX FIFO access Register). */
-#define SACR0_RFTH(x) (x << 12) /* Rx FIFO Interrupt or DMA Trigger
Threshold */
-#define SACR0_TFTH(x) (x << 8) /* Tx FIFO Interrupt or DMA Trigger
Threshold */
+#define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger
Threshold */
+#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger
Threshold */
#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special
Function */
#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
@@ -1682,15 +1682,18 @@
#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte
Interrupt */
#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
-#define SSPSP_DMYSTOP(x) (x << 23) /* Dummy Stop */
-#define SSPSP_SFRMWDTH(x) (x << 16) /* Serial Frame Width */
-#define SSPSP_SFRMDLY(x) (x << 9) /* Serial Frame Delay */
-#define SSPSP_DMYSTRT(x) (x << 7) /* Dummy Start */
-#define SSPSP_STRTDLY(x) (x << 4) /* Start Delay */
+#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
+#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
+#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
+#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
+#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
#define SSPSP_ETDS (1 << 3) /* End of Transfer data
State */
#define SSPSP_SFRMP (1 << 2) /* Serial Frame
Polarity */
-#define SSPSP_SCMODE(x) (x << 0) /* Serial Bit Rate
Clock Mode */
+#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate
Clock Mode */
+#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
+#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
+#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
#define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
#define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
-
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