Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=b37bac94de9ad5eb17bd9327d3ecb6f3b719dc70
Commit: b37bac94de9ad5eb17bd9327d3ecb6f3b719dc70
Parent: dd67b1556ebea118b40986cdb8e70874b5454442
Author: Ralf Baechle <[EMAIL PROTECTED]>
AuthorDate: Sun Oct 14 14:27:18 2007 +0100
Committer: Ralf Baechle <[EMAIL PROTECTED]>
CommitDate: Tue Oct 16 18:23:46 2007 +0100
[MIPS] MSP71XX: Add workarounds file.
Signed-off-by: Ralf Baechle <[EMAIL PROTECTED]>
---
include/asm-mips/pmc-sierra/msp71xx/war.h | 28 ++++++++++++++++++++++++++++
1 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/include/asm-mips/pmc-sierra/msp71xx/war.h
b/include/asm-mips/pmc-sierra/msp71xx/war.h
new file mode 100644
index 0000000..0bf48fc
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/war.h
@@ -0,0 +1,28 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <[EMAIL PROTECTED]>
+ */
+#ifndef __ASM_MIPS_PMC_SIERRA_WAR_H
+#define __ASM_MIPS_PMC_SIERRA_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 0
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#define R10000_LLSC_WAR 0
+#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
+ defined(CONFIG_PMC_MSP7120_FPGA)
+#define MIPS34K_MISSED_ITLB_WAR 1
+#endif
+
+#endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */
-
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