Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=e9c33572a92aa2ee565da5136745ea304ac23d9a
Commit: e9c33572a92aa2ee565da5136745ea304ac23d9a
Parent: 87353d8ac39c52784da605ecbe965ecdfad609ad
Author: Thomas Bogendoerfer <[EMAIL PROTECTED]>
AuthorDate: Mon Nov 26 23:40:01 2007 +0100
Committer: Ralf Baechle <[EMAIL PROTECTED]>
CommitDate: Tue Jan 29 10:14:57 2008 +0000
[MIPS] Use real cache invalidate
R10k non coherent machines need a real dma cache invalidate to get rid of
speculative stores in cache. For other machines this promises a slight
speedup.
Signed-off-by: Thomas Bogendoerfer <[EMAIL PROTECTED]>
Signed-off-by: Ralf Baechle <[EMAIL PROTECTED]>
---
arch/mips/mm/c-r4k.c | 4 ++--
include/asm-mips/r4kcache.h | 7 +++++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index c91b596..0607494 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -589,7 +589,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned
long size)
if (size >= scache_size)
r4k_blast_scache();
else
- blast_scache_range(addr, addr + size);
+ blast_inv_scache_range(addr, addr + size);
return;
}
@@ -597,7 +597,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned
long size)
r4k_blast_dcache();
} else {
R4600_HIT_CACHEOP_WAR_IMPL;
- blast_dcache_range(addr, addr + size);
+ blast_inv_dcache_range(addr, addr + size);
}
bc_inv(addr, size);
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index 2b8466f..4c140db 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -403,6 +403,13 @@ __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I,
Hit_Invalidate_I, 64)
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD,
64)
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD,
128)
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD,
16)
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD,
32)
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD,
64)
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD,
128)
+
/* build blast_xxx_range, protected_blast_xxx_range */
#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
-
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