Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=d1af5b4ea970d8cccdacf243ae42899f3784ad85
Commit:     d1af5b4ea970d8cccdacf243ae42899f3784ad85
Parent:     ab5570f093585a124cd440f5229393e36c5d600e
Author:     Ishizaki Kou <[EMAIL PROTECTED]>
AuthorDate: Wed May 9 17:34:08 2007 +1000
Committer:  Paul Mackerras <[EMAIL PROTECTED]>
CommitDate: Thu May 10 21:28:12 2007 +1000

    [POWERPC] celleb: Fix support for multiple PCI domains
    
    Celleb has multiple PCI host bridges (phbs).  Previous boot logic gives
    non-overlapped bus IDs between PCI host bridges so you can identify
    PHB by bus ID.  But newer boot logic gives same bus ID between PHBs (it
    gives bus ID 0 as root bus.) So we have to set 'phb->buid' as
    non-zero.
    
    Signed-off-by: Kou Ishizaki <[EMAIL PROTECTED]>
    Signed-off-by: Paul Mackerras <[EMAIL PROTECTED]>
---
 arch/powerpc/platforms/celleb/pci.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/platforms/celleb/pci.c 
b/arch/powerpc/platforms/celleb/pci.c
index d1adf34..e9ac19c 100644
--- a/arch/powerpc/platforms/celleb/pci.c
+++ b/arch/powerpc/platforms/celleb/pci.c
@@ -457,6 +457,7 @@ int __devinit celleb_setup_phb(struct pci_controller *phb)
 
        pr_debug("PCI: celleb_setup_phb() %s\n", name);
        phb_set_bus_ranges(dev, phb);
+       phb->buid = 1;
 
        if (strcmp(name, "epci") == 0) {
                phb->ops = &celleb_epci_ops;
-
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