Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=69f4a513911455670d3322fb5252b437c0485707
Commit: 69f4a513911455670d3322fb5252b437c0485707
Parent: e0b2e597d5dd8c4f3778545f65c29a9c6aba0e3a
Author: Ed Lin <[EMAIL PROTECTED]>
AuthorDate: Wed May 9 20:50:37 2007 -0800
Committer: James Bottomley <[EMAIL PROTECTED]>
CommitDate: Wed May 16 12:40:51 2007 -0400
[SCSI] stex: extend hard reset wait time
During hard bus reset of st_shasta controllers, 1 ms is not enough for
16-port controllers, although it's good for 8-port controllers. Extend the
wait time to 100 ms to allow bus resets finish successfully.
Signed-off-by: Ed Lin <[EMAIL PROTECTED]>
Signed-off-by: James Bottomley <[EMAIL PROTECTED]>
---
drivers/scsi/stex.c | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/drivers/scsi/stex.c b/drivers/scsi/stex.c
index 96dcbac..81dd3b7 100644
--- a/drivers/scsi/stex.c
+++ b/drivers/scsi/stex.c
@@ -1041,7 +1041,12 @@ static void stex_hard_reset(struct st_hba *hba)
pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
- msleep(1);
+
+ /*
+ * 1 ms may be enough for 8-port controllers. But 16-port controllers
+ * require more time to finish bus reset. Use 100 ms here for safety
+ */
+ msleep(100);
pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
-
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