Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=569a50ca3f56cd69199733580e7ca0e81029473a
Commit: 569a50ca3f56cd69199733580e7ca0e81029473a
Parent: 0bad33d93af85a445adeedc19c363ef4e492ddd3
Author: Robin Getz <[EMAIL PROTECTED]>
AuthorDate: Wed Nov 21 16:35:57 2007 +0800
Committer: Bryan Wu <[EMAIL PROTECTED]>
CommitDate: Wed Nov 21 16:35:57 2007 +0800
Blackfin arch: Ensure we printk out strings with the proper loglevel
Signed-off-by: Robin Getz <[EMAIL PROTECTED]>
Signed-off-by: Bryan Wu <[EMAIL PROTECTED]>
---
arch/blackfin/kernel/traps.c | 30 +++---
arch/blackfin/mach-common/irqpanic.c | 10 +-
include/asm-blackfin/traps.h | 202 +++++++++++++++++++++-------------
3 files changed, 147 insertions(+), 95 deletions(-)
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index cecf3a2..d88098c 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -250,7 +250,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
case VEC_EXCPT03:
info.si_code = SEGV_STACKFLOW;
sig = SIGSEGV;
- printk(KERN_NOTICE EXC_0x03);
+ printk(KERN_NOTICE EXC_0x03(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
break;
/* 0x04 - User Defined, Caught by default */
@@ -279,7 +279,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
case VEC_OVFLOW:
info.si_code = TRAP_TRACEFLOW;
sig = SIGTRAP;
- printk(KERN_NOTICE EXC_0x11);
+ printk(KERN_NOTICE EXC_0x11(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
break;
/* 0x12 - Reserved, Caught by default */
@@ -301,35 +301,35 @@ asmlinkage void trap_c(struct pt_regs *fp)
case VEC_UNDEF_I:
info.si_code = ILL_ILLOPC;
sig = SIGILL;
- printk(KERN_NOTICE EXC_0x21);
+ printk(KERN_NOTICE EXC_0x21(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
break;
/* 0x22 - Illegal Instruction Combination, handled here */
case VEC_ILGAL_I:
info.si_code = ILL_ILLPARAOP;
sig = SIGILL;
- printk(KERN_NOTICE EXC_0x22);
+ printk(KERN_NOTICE EXC_0x22(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
break;
/* 0x23 - Data CPLB protection violation, handled here */
case VEC_CPLB_VL:
info.si_code = ILL_CPLB_VI;
sig = SIGBUS;
- printk(KERN_NOTICE EXC_0x23);
+ printk(KERN_NOTICE EXC_0x23(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
break;
/* 0x24 - Data access misaligned, handled here */
case VEC_MISALI_D:
info.si_code = BUS_ADRALN;
sig = SIGBUS;
- printk(KERN_NOTICE EXC_0x24);
+ printk(KERN_NOTICE EXC_0x24(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
break;
/* 0x25 - Unrecoverable Event, handled here */
case VEC_UNCOV:
info.si_code = ILL_ILLEXCPT;
sig = SIGILL;
- printk(KERN_NOTICE EXC_0x25);
+ printk(KERN_NOTICE EXC_0x25(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
break;
/* 0x26 - Data CPLB Miss, normal case is handled in _cplb_hdr,
@@ -337,7 +337,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
case VEC_CPLB_M:
info.si_code = BUS_ADRALN;
sig = SIGBUS;
- printk(KERN_NOTICE EXC_0x26);
+ printk(KERN_NOTICE EXC_0x26(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
break;
/* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero, handled here */
@@ -348,7 +348,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
printk(KERN_NOTICE "NULL pointer access (probably)\n");
#else
sig = SIGILL;
- printk(KERN_NOTICE EXC_0x27);
+ printk(KERN_NOTICE EXC_0x27(KERN_NOTICE));
#endif
CHK_DEBUGGER_TRAP();
break;
@@ -356,7 +356,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
case VEC_WATCH:
info.si_code = TRAP_WATCHPT;
sig = SIGTRAP;
- pr_debug(EXC_0x28);
+ pr_debug(EXC_0x28(KERN_DEBUG));
CHK_DEBUGGER_TRAP_MAYBE();
/* Check if this is a watchpoint in kernel space */
if (fp->ipend & 0xffc0)
@@ -378,21 +378,21 @@ asmlinkage void trap_c(struct pt_regs *fp)
case VEC_MISALI_I:
info.si_code = BUS_ADRALN;
sig = SIGBUS;
- printk(KERN_NOTICE EXC_0x2A);
+ printk(KERN_NOTICE EXC_0x2A(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
break;
/* 0x2B - Instruction CPLB protection violation, handled here */
case VEC_CPLB_I_VL:
info.si_code = ILL_CPLB_VI;
sig = SIGBUS;
- printk(KERN_NOTICE EXC_0x2B);
+ printk(KERN_NOTICE EXC_0x2B(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
break;
/* 0x2C - Instruction CPLB miss, handled in _cplb_hdr */
case VEC_CPLB_I_M:
info.si_code = ILL_CPLB_MISS;
sig = SIGBUS;
- printk(KERN_NOTICE EXC_0x2C);
+ printk(KERN_NOTICE EXC_0x2C(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
break;
/* 0x2D - Instruction CPLB Multiple Hits, handled here */
@@ -403,7 +403,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
printk(KERN_NOTICE "Jump to address 0 - 0x0fff\n");
#else
sig = SIGILL;
- printk(KERN_NOTICE EXC_0x2D);
+ printk(KERN_NOTICE EXC_0x2D(KERN_NOTICE));
#endif
CHK_DEBUGGER_TRAP();
break;
@@ -411,7 +411,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
case VEC_ILL_RES:
info.si_code = ILL_PRVOPC;
sig = SIGILL;
- printk(KERN_NOTICE EXC_0x2E);
+ printk(KERN_NOTICE EXC_0x2E(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
break;
/* 0x2F - Reserved, Caught by default */
diff --git a/arch/blackfin/mach-common/irqpanic.c
b/arch/blackfin/mach-common/irqpanic.c
index f05e3da..d62c2e2 100644
--- a/arch/blackfin/mach-common/irqpanic.c
+++ b/arch/blackfin/mach-common/irqpanic.c
@@ -153,21 +153,21 @@ asmlinkage void irq_panic(int reason, struct pt_regs
*regs)
case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR): /* System MMR Error */
info.si_code = BUS_ADRALN;
sig = SIGBUS;
- printk(KERN_EMERG HWC_x2);
+ printk(KERN_EMERG HWC_x2(KERN_EMERG));
break;
case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR): /* External Memory
Addressing Error */
info.si_code = BUS_ADRERR;
sig = SIGBUS;
- printk(KERN_EMERG HWC_x3);
+ printk(KERN_EMERG HWC_x3(KERN_EMERG));
break;
case (SEQSTAT_HWERRCAUSE_PERF_FLOW): /* Performance Monitor
Overflow */
- printk(KERN_EMERG HWC_x12);
+ printk(KERN_EMERG HWC_x12(KERN_EMERG));
break;
case (SEQSTAT_HWERRCAUSE_RAISE_5): /* RAISE 5 instruction
*/
- printk(KERN_EMERG HWC_x18);
+ printk(KERN_EMERG HWC_x18(KERN_EMERG));
break;
default: /* Reserved */
- printk(KERN_EMERG HWC_default);
+ printk(KERN_EMERG HWC_default(KERN_EMERG));
break;
}
}
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
dissimilarity index 70%
index fe365b1..ee1cbf7 100644
--- a/include/asm-blackfin/traps.h
+++ b/include/asm-blackfin/traps.h
@@ -1,75 +1,127 @@
-/*
- * linux/include/asm/traps.h
- *
- * Copyright (C) 1993 Hamish Macdonald
- *
- * Lineo, Inc Jul 2001 Tony Kou
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-#ifndef _BFIN_TRAPS_H
-#define _BFIN_TRAPS_H
-
-#define VEC_SYS (0)
-#define VEC_EXCPT01 (1)
-#define VEC_EXCPT02 (2)
-#define VEC_EXCPT03 (3)
-#define VEC_EXCPT04 (4)
-#define VEC_EXCPT05 (5)
-#define VEC_EXCPT06 (6)
-#define VEC_EXCPT07 (7)
-#define VEC_EXCPT08 (8)
-#define VEC_EXCPT09 (9)
-#define VEC_EXCPT10 (10)
-#define VEC_EXCPT11 (11)
-#define VEC_EXCPT12 (12)
-#define VEC_EXCPT13 (13)
-#define VEC_EXCPT14 (14)
-#define VEC_EXCPT15 (15)
-#define VEC_STEP (16)
-#define VEC_OVFLOW (17)
-#define VEC_UNDEF_I (33)
-#define VEC_ILGAL_I (34)
-#define VEC_CPLB_VL (35)
-#define VEC_MISALI_D (36)
-#define VEC_UNCOV (37)
-#define VEC_CPLB_M (38)
-#define VEC_CPLB_MHIT (39)
-#define VEC_WATCH (40)
-#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
-#define VEC_MISALI_I (42)
-#define VEC_CPLB_I_VL (43)
-#define VEC_CPLB_I_M (44)
-#define VEC_CPLB_I_MHIT (45)
-#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
-
-#ifndef __ASSEMBLY__
-
-#define HWC_x2 "System MMR Error\nAn error occurred due to an invalid access
to an System MMR location\nPossible reason: a 32-bit register is accessed with
a 16-bit instruction,\nor a 16-bit register is accessed with a 32-bit
instruction.\n"
-#define HWC_x3 "External Memory Addressing Error\n"
-#define HWC_x12 "Performance Monitor Overflow\n"
-#define HWC_x18 "RAISE 5 instruction\n Software issued a RAISE 5 instruction
to invoke the Hardware\n"
-#define HWC_default "Reserved\n"
-
-#define EXC_0x03 "Application stack overflow\n - Please increase the stack
size of the application using elf2flt -s option,\n and/or reduce the stack use
of the application.\n"
-#define EXC_0x10 "Single step\n - When the processor is in single step mode,
every instruction\n generates an exception. Primarily used for debugging.\n"
-#define EXC_0x11 "Exception caused by a trace buffer full condition\n - The
processor takes this exception when the trace\n buffer overflows (only when
enabled by the Trace Unit Control register).\n"
-#define EXC_0x21 "Undefined instruction\n - May be used to emulate
instructions that are not defined for\n a particular processor
implementation.\n"
-#define EXC_0x22 "Illegal instruction combination\n - See section for
multi-issue rules in the ADSP-BF53x Blackfin\n Processor Instruction Set
Reference.\n"
-#define EXC_0x23 "Data access CPLB protection violation\n - Attempted read or
write to Supervisor resource,\n or illegal data memory access. \n"
-#define EXC_0x24 "Data access misaligned address violation\n - Attempted
misaligned data memory or data cache access.\n"
-#define EXC_0x25 "Unrecoverable event\n - For example, an exception generated
while processing a previous exception.\n"
-#define EXC_0x26 "Data access CPLB miss\n - Used by the MMU to signal a CPLB
miss on a data access.\n"
-#define EXC_0x27 "Data access multiple CPLB hits\n - More than one CPLB entry
matches data fetch address.\n"
-#define EXC_0x28 "Program Sequencer Exception caused by an emulation
watchpoint match\n - There is a watchpoint match, and one of the EMUSW\n bits
in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
-#define EXC_0x2A "Instruction fetch misaligned address violation\n - Attempted
misaligned instruction cache fetch. On a misaligned instruction fetch
exception,\n the return address provided in RETX is the destination address
which is misaligned, rather than the address of the offending instruction.\n"
-#define EXC_0x2B "CPLB protection violation\n - Illegal instruction fetch
access (memory protection violation).\n"
-#define EXC_0x2C "Instruction fetch CPLB miss\n - CPLB miss on an instruction
fetch.\n"
-#define EXC_0x2D "Instruction fetch multiple CPLB hits\n - More than one CPLB
entry matches instruction fetch address.\n"
-#define EXC_0x2E "Illegal use of supervisor resource\n - Attempted to use a
Supervisor register or instruction from User mode.\n Supervisor resources are
registers and instructions that are reserved\n for Supervisor use: Supervisor
only registers, all MMRs, and Supervisor\n only instructions.\n"
-
-#endif /* __ASSEMBLY__ */
-#endif /* _BFIN_TRAPS_H */
+/*
+ * linux/include/asm/traps.h
+ *
+ * Copyright (C) 1993 Hamish Macdonald
+ *
+ * Lineo, Inc Jul 2001 Tony Kou
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _BFIN_TRAPS_H
+#define _BFIN_TRAPS_H
+
+#define VEC_SYS (0)
+#define VEC_EXCPT01 (1)
+#define VEC_EXCPT02 (2)
+#define VEC_EXCPT03 (3)
+#define VEC_EXCPT04 (4)
+#define VEC_EXCPT05 (5)
+#define VEC_EXCPT06 (6)
+#define VEC_EXCPT07 (7)
+#define VEC_EXCPT08 (8)
+#define VEC_EXCPT09 (9)
+#define VEC_EXCPT10 (10)
+#define VEC_EXCPT11 (11)
+#define VEC_EXCPT12 (12)
+#define VEC_EXCPT13 (13)
+#define VEC_EXCPT14 (14)
+#define VEC_EXCPT15 (15)
+#define VEC_STEP (16)
+#define VEC_OVFLOW (17)
+#define VEC_UNDEF_I (33)
+#define VEC_ILGAL_I (34)
+#define VEC_CPLB_VL (35)
+#define VEC_MISALI_D (36)
+#define VEC_UNCOV (37)
+#define VEC_CPLB_M (38)
+#define VEC_CPLB_MHIT (39)
+#define VEC_WATCH (40)
+#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
+#define VEC_MISALI_I (42)
+#define VEC_CPLB_I_VL (43)
+#define VEC_CPLB_I_M (44)
+#define VEC_CPLB_I_MHIT (45)
+#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
+
+#ifndef __ASSEMBLY__
+
+#define HWC_x2(level) \
+ "System MMR Error\n" \
+ level " - An error occurred due to an invalid access to an System MMR
location\n" \
+ level " Possible reason: a 32-bit register is accessed with a 16-bit
instruction\n" \
+ level " or a 16-bit register is accessed with a 32-bit instruction.\n"
+#define HWC_x3(level) \
+ "External Memory Addressing Error\n"
+#define HWC_x12(level) \
+ "Performance Monitor Overflow\n"
+#define HWC_x18(level) \
+ "RAISE 5 instruction\n" \
+ level " Software issued a RAISE 5 instruction to invoke the
Hardware\n"
+#define HWC_default(level) \
+ "Reserved\n"
+#define EXC_0x03(level) \
+ "Application stack overflow\n" \
+ level " - Please increase the stack size of the application using
elf2flt -s option,\n" \
+ level " and/or reduce the stack use of the application.\n"
+#define EXC_0x10(level) \
+ "Single step\n" \
+ level " - When the processor is in single step mode, every
instruction\n" \
+ level " generates an exception. Primarily used for debugging.\n"
+#define EXC_0x11(level) \
+ "Exception caused by a trace buffer full condition\n" \
+ level " - The processor takes this exception when the trace\n" \
+ level " buffer overflows (only when enabled by the Trace Unit Control
register).\n"
+#define EXC_0x21(level) \
+ "Undefined instruction\n" \
+ level " - May be used to emulate instructions that are not defined
for\n" \
+ level " a particular processor implementation.\n"
+#define EXC_0x22(level) \
+ "Illegal instruction combination\n" \
+ level " - See section for multi-issue rules in the ADSP-BF53x
Blackfin\n" \
+ level " Processor Instruction Set Reference.\n"
+#define EXC_0x23(level) \
+ "Data access CPLB protection violation\n" \
+ level " - Attempted read or write to Supervisor resource,\n" \
+ level " or illegal data memory access. \n"
+#define EXC_0x24(level) \
+ "Data access misaligned address violation\n" \
+ level " - Attempted misaligned data memory or data cache access.\n"
+#define EXC_0x25(level) \
+ "Unrecoverable event\n" \
+ level " - For example, an exception generated while processing a
previous exception.\n"
+#define EXC_0x26(level) \
+ "Data access CPLB miss\n" \
+ level " - Used by the MMU to signal a CPLB miss on a data access.\n"
+#define EXC_0x27(level) \
+ "Data access multiple CPLB hits\n" \
+ level " - More than one CPLB entry matches data fetch address.\n"
+#define EXC_0x28(level) \
+ "Program Sequencer Exception caused by an emulation watchpoint match\n"
\
+ level " - There is a watchpoint match, and one of the EMUSW\n" \
+ level " bits in the Watchpoint Instruction Address Control register
(WPIACTL) is set.\n"
+#define EXC_0x2A(level) \
+ "Instruction fetch misaligned address violation\n" \
+ level " - Attempted misaligned instruction cache fetch. On a misaligned
instruction fetch\n" \
+ level " exception, the return address provided in RETX is the
destination address which is\n" \
+ level " misaligned, rather than the address of the offending
instruction.\n"
+#define EXC_0x2B(level) \
+ "CPLB protection violation\n" \
+ level " - Illegal instruction fetch access (memory protection
violation).\n"
+#define EXC_0x2C(level) \
+ "Instruction fetch CPLB miss\n" \
+ level " - CPLB miss on an instruction fetch.\n"
+#define EXC_0x2D(level) \
+ "Instruction fetch multiple CPLB hits\n" \
+ level " - More than one CPLB entry matches instruction fetch address.\n"
+#define EXC_0x2E(level) \
+ "Illegal use of supervisor resource\n" \
+ level " - Attempted to use a Supervisor register or instruction from
User mode.\n" \
+ level " Supervisor resources are registers and instructions that are
reserved\n" \
+ level " for Supervisor use: Supervisor only registers, all MMRs, and
Supervisor\n" \
+ level " only instructions.\n"
+
+#endif /* __ASSEMBLY__ */
+#endif /* _BFIN_TRAPS_H */
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