Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=60e9356d770ca3622fe5e84680b78fc376e53fbf
Commit: 60e9356d770ca3622fe5e84680b78fc376e53fbf
Parent: 1aafd9091226a02b481298315f959f777294684e
Author: Mike Frysinger <[EMAIL PROTECTED]>
AuthorDate: Wed Jul 25 11:56:01 2007 +0800
Committer: Bryan Wu <[EMAIL PROTECTED]>
CommitDate: Wed Jul 25 11:56:01 2007 +0800
Blackfin arch: update BF54x anomaly list
Signed-off-by: Mike Frysinger <[EMAIL PROTECTED]>
Signed-off-by: Roy Huang <[EMAIL PROTECTED]>
Signed-off-by: Bryan Wu <[EMAIL PROTECTED]>
---
include/asm-blackfin/mach-bf548/anomaly.h | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h
b/include/asm-blackfin/mach-bf548/anomaly.h
index 952f03e..37e0bd2 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -27,6 +27,8 @@
#define ANOMALY_05000265 (1)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
+/* False Hardware Error Exception when ISR context is not restored */
+#define ANOMALY_05000281 (1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory
*/
#define ANOMALY_05000310 (1)
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are
Interrupted */
@@ -59,6 +61,7 @@
#define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000244 (0)
+#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
-
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