Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=17304383ebc1ce68a88030ac4d18ea549d9578c7
Commit: 17304383ebc1ce68a88030ac4d18ea549d9578c7
Parent: d0aff6e6f4e54f79f9c89d147d371bad384454e9
Author: Brian Gerst <[EMAIL PROTECTED]>
AuthorDate: Mon May 21 14:31:53 2007 +0200
Committer: Linus Torvalds <[EMAIL PROTECTED]>
CommitDate: Mon May 21 09:56:57 2007 -0700
i386: fix PGE mask
cr4 is a 32-bit register, so casting the mask to an unsigned char is wrong,
as it clears more than the PGE bit.
Signed-off-by: Brian Gerst <[EMAIL PROTECTED]>
Signed-off-by: Andi Kleen <[EMAIL PROTECTED]>
Signed-off-by: Linus Torvalds <[EMAIL PROTECTED]>
---
arch/i386/kernel/cpu/mtrr/cyrix.c | 2 +-
arch/i386/kernel/cpu/mtrr/state.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/i386/kernel/cpu/mtrr/cyrix.c
b/arch/i386/kernel/cpu/mtrr/cyrix.c
index 0737a59..9edf562 100644
--- a/arch/i386/kernel/cpu/mtrr/cyrix.c
+++ b/arch/i386/kernel/cpu/mtrr/cyrix.c
@@ -136,7 +136,7 @@ static void prepare_set(void)
/* Save value of CR4 and clear Page Global Enable (bit 7) */
if ( cpu_has_pge ) {
cr4 = read_cr4();
- write_cr4(cr4 & (unsigned char) ~(1 << 7));
+ write_cr4(cr4 & ~X86_CR4_PGE);
}
/* Disable and flush caches. Note that wbinvd flushes the TLBs as
diff --git a/arch/i386/kernel/cpu/mtrr/state.c
b/arch/i386/kernel/cpu/mtrr/state.c
index f62ecd1..7b39a2f 100644
--- a/arch/i386/kernel/cpu/mtrr/state.c
+++ b/arch/i386/kernel/cpu/mtrr/state.c
@@ -19,7 +19,7 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
/* Save value of CR4 and clear Page Global Enable (bit 7) */
if ( cpu_has_pge ) {
ctxt->cr4val = read_cr4();
- write_cr4(ctxt->cr4val & (unsigned char) ~(1 << 7));
+ write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
}
/* Disable and flush caches. Note that wbinvd flushes the TLBs
as
-
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