Gitweb: http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=3a9e3a51dd47bd9e2fd6bcf3c893eb5729c6f1ee Commit: 3a9e3a51dd47bd9e2fd6bcf3c893eb5729c6f1ee Parent: 0c173174d0e8267b1100442f4df119ab6d52821c Author: Tejun Heo <[EMAIL PROTECTED]> AuthorDate: Tue Oct 23 15:27:31 2007 +0900 Committer: Jeff Garzik <[EMAIL PROTECTED]> CommitDate: Tue Oct 23 21:20:02 2007 -0400
jmicron: update quirk for JMB361/3/5/6 Set bits 0, 4, 5 and 7 of PCI configuration register 0x40 in the quirk. This has the following effects and is recommended by the vendor. * Force enable of IDE channels (used to be left alone as BIOS configured) * Change initial phase behavior of PIO cycle such that the host pulls down the bus instead of tristating it. Vendor recommends this setting. The above settings are better for the current generation of controllers and needed for the upcoming next generation. Tested on JMB363. Signed-off-by: Tejun Heo <[EMAIL PROTECTED]> Cc: Ethan Hsiao <[EMAIL PROTECTED]> Signed-off-by: Jeff Garzik <[EMAIL PROTECTED]> --- drivers/pci/quirks.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 59d4da2..d0bb5b9 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -1230,7 +1230,7 @@ static void quirk_jmicron_ata(struct pci_dev *pdev) case PCI_DEVICE_ID_JMICRON_JMB363: /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ /* Set the class codes correctly and then direct IDE 0 */ - conf1 |= 0x00C2A102; /* Set 1, 8, 13, 15, 17, 22, 23 */ + conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ break; case PCI_DEVICE_ID_JMICRON_JMB368: - To unsubscribe from this list: send the line "unsubscribe git-commits-head" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html