Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=8c781bf77a339748839bfd5eedfe2ad3e0e05c4a
Commit:     8c781bf77a339748839bfd5eedfe2ad3e0e05c4a
Parent:     abcdceb9d0bf39da7c7ff8bcdff6eb4d9dfec56f
Author:     Albert Lee <[EMAIL PROTECTED]>
AuthorDate: Tue Jun 26 13:43:15 2007 +0800
Committer:  Jeff Garzik <[EMAIL PROTECTED]>
CommitDate: Mon Jul 2 10:12:34 2007 -0400

    libata: pata_pdc2027x PLL input clock fix
    
    Recently the PLL input clock of pata_pdc2027x is sometimes detected
    higer than expected (e.g. 20.027 MHz compared to 16.714 MHz).
    It seems sometimes the mdelay() function is not as precise as it
    used to be. Per Alan's advice, HT or power management might affect
    the precision of mdelay().
    
    This patch calls gettimeofday() to mesure the time elapsed and
    calculate the PLL input clock accordingly.
    
    Signed-off-by: Albert Lee <[EMAIL PROTECTED]>
    Cc: Alan Cox <[EMAIL PROTECTED]>
    Signed-off-by: Jeff Garzik <[EMAIL PROTECTED]>
---
 drivers/ata/pata_pdc2027x.c |   11 +++++++++--
 1 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c
index 0d2cc49..69a5aa4 100644
--- a/drivers/ata/pata_pdc2027x.c
+++ b/drivers/ata/pata_pdc2027x.c
@@ -689,10 +689,12 @@ static long pdc_detect_pll_input_clock(struct ata_host 
*host)
        void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
        u32 scr;
        long start_count, end_count;
-       long pll_clock;
+       struct timeval start_time, end_time;
+       long pll_clock, usec_elapsed;
 
        /* Read current counter value */
        start_count = pdc_read_counter(host);
+       do_gettimeofday(&start_time);
 
        /* Start the test mode */
        scr = readl(mmio_base + PDC_SYS_CTL);
@@ -705,6 +707,7 @@ static long pdc_detect_pll_input_clock(struct ata_host 
*host)
 
        /* Read the counter values again */
        end_count = pdc_read_counter(host);
+       do_gettimeofday(&end_time);
 
        /* Stop the test mode */
        scr = readl(mmio_base + PDC_SYS_CTL);
@@ -713,7 +716,11 @@ static long pdc_detect_pll_input_clock(struct ata_host 
*host)
        readl(mmio_base + PDC_SYS_CTL); /* flush */
 
        /* calculate the input clock in Hz */
-       pll_clock = (start_count - end_count) * 10;
+       usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
+               (end_time.tv_usec - start_time.tv_usec);
+
+       pll_clock = (start_count - end_count) / 100 *
+               (100000000 / usec_elapsed);
 
        PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
        PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
-
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