Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=7de970e11fb832a56c897276967fb0e49f59b313
Commit:     7de970e11fb832a56c897276967fb0e49f59b313
Parent:     5278b50cea851d8264b7b28212a483328650476f
Author:     Nate Dailey <[EMAIL PROTECTED]>
AuthorDate: Thu Feb 15 18:13:46 2007 -0500
Committer:  Jeff Garzik <[EMAIL PROTECTED]>
CommitDate: Thu Feb 15 18:13:46 2007 -0500

    sata_vsc: use default cache line size if non-zero
    
    This modifies drivers/ata/sata_vsc.c to only set the cache line size
    to 0x80 if the default value is zero. Apparently zero isn't allowed
    due to a bug in the chip, but I've found performance is much better
    with the (non-zero) default instead of 0x80.
    
    [note1: "default" means BIOS-programmed value, in this context -jgarzik]
    
    [note2: superfluous braces were removed from the patch -jg]
    
    Signed-off-by: Nate Dailey <[EMAIL PROTECTED]>
    Signed-off-by: Jeremy Higdon <[EMAIL PROTECTED]>
    Signed-off-by: Jeff Garzik <[EMAIL PROTECTED]>
---
 drivers/ata/sata_vsc.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/sata_vsc.c b/drivers/ata/sata_vsc.c
index 3d9daf2..2fd037b 100644
--- a/drivers/ata/sata_vsc.c
+++ b/drivers/ata/sata_vsc.c
@@ -346,6 +346,7 @@ static int __devinit vsc_sata_init_one (struct pci_dev 
*pdev, const struct pci_d
        struct ata_probe_ent *probe_ent;
        void __iomem *mmio_base;
        int rc;
+       u8 cls;
 
        if (!printed_version++)
                dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
@@ -383,9 +384,12 @@ static int __devinit vsc_sata_init_one (struct pci_dev 
*pdev, const struct pci_d
        INIT_LIST_HEAD(&probe_ent->node);
 
        /*
-        * Due to a bug in the chip, the default cache line size can't be used
+        * Due to a bug in the chip, the default cache line size can't be
+        * used (unless the default is non-zero).
         */
-       pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
+       pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
+       if (cls == 0x00)
+               pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
 
        if (pci_enable_msi(pdev) == 0)
                pci_intx(pdev, 0);
-
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