Gitweb:
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=8f70920f2f2a699b4ad35e625071cd92f4ba6ca3
Commit: 8f70920f2f2a699b4ad35e625071cd92f4ba6ca3
Parent: 451af33552286b426940a32126bd3ece243223a3
Author: Stephen Hemminger <[EMAIL PROTECTED]>
AuthorDate: Mon Jun 4 17:23:25 2007 -0700
Committer: Jeff Garzik <[EMAIL PROTECTED]>
CommitDate: Sun Jul 8 22:16:42 2007 -0400
sky2: GPIO register
The General Purpose I/O register is yet another hardware workaround
catchall. Enable workaround that vendor driver does to stay
but for bug compatiable.
Signed-off-by: Stephen Hemminger <[EMAIL PROTECTED]>
Signed-off-by: Jeff Garzik <[EMAIL PROTECTED]>
---
drivers/net/sky2.c | 5 +++++
drivers/net/sky2.h | 14 ++++++++++++++
2 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index fbe39d9..1f1b6db 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -230,6 +230,11 @@ static void sky2_power_on(struct sky2_hw *hw)
sky2_pci_write32(hw, PCI_DEV_REG5, reg);
sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
+
+ /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
+ reg = sky2_read32(hw, B2_GP_IO);
+ reg |= GLB_GPIO_STAT_RACE_DIS;
+ sky2_write32(hw, B2_GP_IO, reg);
}
}
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 00907f5..c6c0baf 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -441,6 +441,20 @@ enum {
TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
};
+/* B2_GPIO */
+enum {
+ GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */
+ GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */
+
+ GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to
D0 */
+ GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */
+ GLB_GPIO_STAT_RACE_DIS = 1<<13, /* Status Race Disable */
+ GLB_GPIO_TEST_SEL_MSK = 3<<11, /* Testmode Select */
+ GLB_GPIO_TEST_SEL_BASE = 1<<11,
+ GLB_GPIO_RAND_ENA = 1<<10, /* Random Enable */
+ GLB_GPIO_RAND_BIT_1 = 1<<9, /* Random Bit 1 */
+};
+
/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
enum {
CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
-
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