[Github-comments] Re: [geany/geany] SystemVerilog filetype syntax highlighting (Issue #3511)

2023-09-23 Thread elextr via Github-comments
> I don't know what's the policy on file extensions in this project; is it OK > to add file extensions even if they're not exactly the same file type? To emphasise, adding an extension tells Geany to treat `*.sv` files as Verilog, not that Geany supports SystemVerilog. Probably better would be

[Github-comments] Re: [geany/geany] SystemVerilog filetype syntax highlighting (Issue #3511)

2023-09-23 Thread cousteau via Github-comments
You can add the `*.sv` extension for Verilog in Tools > Configuration Files > file_extensions.conf, so that whenever you open a .sv file in Geany it gets detected and highlighted as a Verilog file. But I'm not sure having Geany include that extension association by default would be a good idea.

[Github-comments] Re: [geany/geany] SystemVerilog filetype syntax highlighting (Issue #3511)

2023-06-01 Thread elextr via Github-comments
What filetype are you editing the `.sv` files as? -- Reply to this email directly or view it on GitHub: https://github.com/geany/geany/issues/3511#issuecomment-1572914385 You are receiving this because you are subscribed to this thread. Message ID: