This is interesting, even for software jocks like me. But I take time to
notice also, with some amusement, the slanted language toward Apple and away
from Intel and AMD. Calling it "conflict" when he means Intel and AMD might do
it differently, for example. Still interesting.
---
Bob Bridges
s://www.theregister.com/2020/11/19/apple_m1_high_bandwidth_memory_performance/
> >
> >
> >
> >> --
> >> Shmuel (Seymour J.) Metz
> >> http://mason.gmu.edu/~smetz3
> >>
> >>
> >> From: IBM Mainframe Discussion List [IBM-MAIN
tp://mason.gmu.edu/~smetz3
From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU]
on behalf of Steve Thompson [ste...@wkyr.net]
Sent: Tuesday, May 23, 2023 1:50 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Architectural questions [WAS: Are Banks
-MAIN@LISTSERV.UA.EDU] on behalf of
Steve Thompson [ste...@wkyr.net]
Sent: Tuesday, May 23, 2023 1:50 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Architectural questions [WAS: Are Banks Breaking Up With
Mainframes? | Forbes]
I'm not asking about cache lines, necessarily.
With the G3 chip se
Thompson [ste...@wkyr.net]
Sent: Tuesday, May 23, 2023 1:50 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Architectural questions [WAS: Are Banks Breaking Up With
Mainframes? | Forbes]
I'm not asking about cache lines, necessarily.
With the G3 chip set, as I recall, it had 256 byte wide cache
I'm not asking about cache lines, necessarily.
With the G3 chip set, as I recall, it had 256 byte wide cache
lines, and CPU <-> C-store was using a 256 byte bus while the
IOPs <-> C-store were using a 64 byte bus.
What makes one system faster than the other has to do with
clocking and bus wi
I’ve just realised that I was confused. Steven, can your confirm that that bus
width between the memory controller and CPU was 256 bytes (not bits)? On a G3
9672?
> On 23 May 2023, at 8:48 am, David Crayford wrote:
>
> Good question. By bus size I'm assuming that your referring to cache-lines?
Good question. By bus size I'm assuming that your referring to
cache-lines? I wonder how much of a difference that makes with OOO
pipelines? What I can confirm is that my new Arm M2 MacBook Pro which
has a 32-byte cache-line sizes absolutely smashes my AMD Ryzen 5 in
Cinebench benchmarks.
On
I have a question about these systems, both z and not z.
What is the current bus width supported?
At the G3 level for "z" the CPU-RAM bus was 256 bytes wide, as I
recall.
For IOP to RAM it was 64 bytes wide.
For the systems I run (off the shelf stuff for Linux and windows)
the bus is still
