A nagging doubt since my earlier post compelled me to go look at the
UCB mapping. It seems that the bit is actually a one-byte count
which makes sense for concurrent RESERVE activity.
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Date: Sun, 1 Jul 2012 00:28:04 -0400
From: shmuel+...@patriot.net
Subject: Re: SV: Why is GRS ENQ
In bay145-w28ad40f15a4f1654e89483a3...@phx.gbl, on 06/25/2012
at 09:25 AM, J R jayare...@hotmail.com said:
The RESERVE macro did (still does?) not directly do the hardware
reserve. Rather, it set a bit in the UCB to tell the next IO to the
unit to prepend a reserve CCW to the channel
