Re: XLC inline assembler question

2023-05-03 Thread Phil Smith III
Thanks to all for the info!

 

(Summary for the assembler list, since the action was all on IBM-MAIN: It won't 
hurt; might affect optimization slightly, but probably not worth worrying 
about.)


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Re: XLC inline assembler question

2023-05-02 Thread Linda Chui
On Mon, 1 May 2023 18:18:38 -0400, Phil Smith III  wrote:

>Doh, I of course meant -qasm not -dasm. 
>
> 
>
>From: Phil Smith III  
>Sent: Monday, May 1, 2023 5:02 PM
>To: ibm-m...@bama.ua.edu; IBM Mainframe Assembler List 
>(assembler-l...@listserv.uga.edu) 
>Subject: XLC inline assembler question
>
> 
>
>(Cross-posted to IBM-MAIN and the assembler list)
>
>When compiling C programs with XLC, you need to specify the -dasm flag to have 
>inline assembler code recognized as such. I can see PoE arguments for 
>requiring that option; what isn't clear is whether there's any downside to it 
>beyond the unlikely case that you decide to have a function of your own named 
>asm or __asm or __asm__. Is there? We'd rather just use it all the time, 
>rather than trying to keep track of which modules have inline assembler and 
>which don't, but not if it's going to cost significant performance at compile 
>time or something.
>
>
>--
>For IBM-MAIN subscribe / signoff / archive access instructions,
>send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN

(posting on behalf of a colleague)

hi Phil,

Generally there is no downside for specifying -qasm all the time. Your analysis 
(and Paul’s) is correct.
There are a few side issues (listings changing to show ASM is in effect, etc.), 
but just turning that option on for everything should work as long as you don’t 
mind those changes occurring.

hope this helps.

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Re: XLC inline assembler question

2023-05-01 Thread Paul Gilmartin
On Mon, 1 May 2023 17:02:23 -0400, Phil Smith III wrote:
>(Cross-posted to IBM-MAIN and the assembler list)
>
>...; what isn't clear is whether there's any downside to it beyond the 
>unlikely case that you decide to have a function of your own named asm or 
>__asm or __asm__. Is there? 
> 
I believe the ANSI standard reserves names beginning with "__" for
the implementation.  However a FOSS provider whom I once scolded 
for using using such a name replied, "I *am* the implementation!"

-- 
gil

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Re: XLC inline assembler question

2023-05-01 Thread Phil Smith III
Doh, I of course meant -qasm not -dasm. 

 

From: Phil Smith III  
Sent: Monday, May 1, 2023 5:02 PM
To: ibm-m...@bama.ua.edu; IBM Mainframe Assembler List 
(assembler-l...@listserv.uga.edu) 
Subject: XLC inline assembler question

 

(Cross-posted to IBM-MAIN and the assembler list)

When compiling C programs with XLC, you need to specify the -dasm flag to have 
inline assembler code recognized as such. I can see PoE arguments for requiring 
that option; what isn't clear is whether there's any downside to it beyond the 
unlikely case that you decide to have a function of your own named asm or __asm 
or __asm__. Is there? We'd rather just use it all the time, rather than trying 
to keep track of which modules have inline assembler and which don't, but not 
if it's going to cost significant performance at compile time or something.


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XLC inline assembler question

2023-05-01 Thread Phil Smith III
(Cross-posted to IBM-MAIN and the assembler list)

When compiling C programs with XLC, you need to specify the -dasm flag to have 
inline assembler code recognized as such. I can see PoE arguments for requiring 
that option; what isn't clear is whether there's any downside to it beyond the 
unlikely case that you decide to have a function of your own named asm or __asm 
or __asm__. Is there? We'd rather just use it all the time, rather than trying 
to keep track of which modules have inline assembler and which don't, but not 
if it's going to cost significant performance at compile time or something.




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Re: Assembler question

2020-07-06 Thread Mike Schwab
01 records start on a double word boundary x'0' or x'8' as the last digit.
77 independent items are sorted by multiple of 8 byte items, 4 bytes
items, 2 bytes items, odd number of bytes items.

On Mon, Jul 6, 2020 at 10:00 AM Binyamin Dissen
 wrote:
>
> Then one wonders what "aligned" means to you.
>
> On Mon, 6 Jul 2020 02:37:22 + "Gibney, Dave"  wrote:
>
> :>Actually, it is. But,  BLA-2 below is still offset 3 bytes from BLA-RECORD 
> because BLA-1 is only 3 bytes long
> :>
> :>> -Original Message-
> :>> From: IBM Mainframe Discussion List  On
> :>> Behalf Of Joe Monk
> :>> Sent: Sunday, July 05, 2020 4:38 PM
> :>> To: IBM-MAIN@LISTSERV.UA.EDU
> :>> Subject: Re: Assembler question
> :>>
> :>> 01 BLA-RECORD.
> :>> 05 BLA-RECORD PIC X(4).
> :>> 05 BLA-RECOR2 REDEFINES BLA-RECORD PIC X(3).
> :>>
> :>> The 01 is aligned.
> :>> The 05 is aligned.
> :>> The second 05 is not aligned.
> :>>
> :>> Joe
> :>>
> :>>
> :>> On Sun, Jul 5, 2020 at 6:27 PM Binyamin Dissen
> :>> 
> :>> wrote:
> :>>
> :>> > 01   BLA-RECORD.
> :>> >05   BLA-1  PIC X(3).
> :>> >05   BLA-2  PIC S9(8) COMP.
> :>> >
> :>> > Do you truly wish to assert that BLA-2 is aligned?
> :>> >
> :>> > On Sun, 5 Jul 2020 17:45:37 -0500 Joe Monk 
> :>> wrote:
> :>> >
> :>> > :>"Subordinate items are not aligned"
> :>> > :>
> :>> > :>yeah, no.
> :>> > :>
> :>> > :>If an 01 is aligned, then the subordinate 05 under the 01 is also
> :>> > aligned.
> :>> > :>It has to be this way because of REDEFINES. I cant REDEFINE an 
> unaligned
> :>> > :>item into an aligned item.
> :>> > :>
> :>> > :>77 are aligned because they are standalone, i.e. no grouping.
> :>> > :>
> :>> > :>Joe
> :>> > :>
> :>> > :>On Sun, Jul 5, 2020 at 12:07 PM Binyamin Dissen <
> :>> > bdis...@dissensoftware.com>
> :>> > :>wrote:
> :>> > :>
> :>> > :>> On Sun, 5 Jul 2020 11:31:55 -0500 Joe Monk
> :>> 
> :>> > wrote:
> :>> > :>>
> :>> > :>> :>Cobol has alignment too. You just dont see it.
> :>> > :>>
> :>> > :>> :>All storage is aligned.
> :>> > :>>
> :>> > :>> The opposite is true.
> :>> > :>>
> :>> > :>> Group (01/77) are aligned.
> :>> > :>>
> :>> > :>> Subordinate items are not aligned unless the SYNC clause is 
> specified.
> :>> > :>>
> :>> > :>> :>On Sun, Jul 5, 2020 at 10:24 AM Nguyen Dt 
> :>> wrote:
> :>> > :>> :>
> :>> > :>> :>> Thank you all for your inputs,
> :>> > :>> :>>
> :>> > :>> :>> I am over the problem now.
> :>> > :>> :>> In fact what i tried to do is to Move some fields to my output
> :>> > fields
> :>> > :>> and
> :>> > :>> :>> then write it as a report. (It is a Db2 performance report, the
> :>> > input
> :>> > :>> are
> :>> > :>> :>> from the trace buffers with the macros given by Db2 libraries)
> :>> > :>> :>>
> :>> > :>> :>> So my program is roughly like this
> :>> > :>> :>> READ Buffer on QW... variables
> :>> > :>> :>>
> :>> > :>> :>> MVC OW...,QW...
> :>> > :>> :>>
> :>> > :>> :>>
> :>> > :>> :>> OW... are the output fields i defined it exactly as in the DSECT
> :>> > got
> :>> > :>> from
> :>> > :>> :>> the macros.
> :>> > :>> :>> As it is an output field, the position is important  (and it is
> :>> > why i
> :>> > :>> :>> detected a problem in the positions of my fields)
> :>> > :>> :>> Its is OK now with OW... variables defined as characters CLx
> :>> > :>> :>>
> :>> > :>> :>> (PS: When i use NOALIGN , the program abends at execution ...)
> :>> > :>> :>>
> :>> > :>>

Re: Assembler question

2020-07-06 Thread Binyamin Dissen
Then one wonders what "aligned" means to you.

On Mon, 6 Jul 2020 02:37:22 + "Gibney, Dave"  wrote:

:>Actually, it is. But,  BLA-2 below is still offset 3 bytes from BLA-RECORD 
because BLA-1 is only 3 bytes long
:>
:>> -Original Message-
:>> From: IBM Mainframe Discussion List  On
:>> Behalf Of Joe Monk
:>> Sent: Sunday, July 05, 2020 4:38 PM
:>> To: IBM-MAIN@LISTSERV.UA.EDU
:>> Subject: Re: Assembler question
:>> 
:>> 01 BLA-RECORD.
:>> 05 BLA-RECORD PIC X(4).
:>> 05 BLA-RECOR2 REDEFINES BLA-RECORD PIC X(3).
:>> 
:>> The 01 is aligned.
:>> The 05 is aligned.
:>> The second 05 is not aligned.
:>> 
:>> Joe
:>> 
:>> 
:>> On Sun, Jul 5, 2020 at 6:27 PM Binyamin Dissen
:>> 
:>> wrote:
:>> 
:>> > 01   BLA-RECORD.
:>> >05   BLA-1  PIC X(3).
:>> >05   BLA-2  PIC S9(8) COMP.
:>> >
:>> > Do you truly wish to assert that BLA-2 is aligned?
:>> >
:>> > On Sun, 5 Jul 2020 17:45:37 -0500 Joe Monk 
:>> wrote:
:>> >
:>> > :>"Subordinate items are not aligned"
:>> > :>
:>> > :>yeah, no.
:>> > :>
:>> > :>If an 01 is aligned, then the subordinate 05 under the 01 is also
:>> > aligned.
:>> > :>It has to be this way because of REDEFINES. I cant REDEFINE an unaligned
:>> > :>item into an aligned item.
:>> > :>
:>> > :>77 are aligned because they are standalone, i.e. no grouping.
:>> > :>
:>> > :>Joe
:>> > :>
:>> > :>On Sun, Jul 5, 2020 at 12:07 PM Binyamin Dissen <
:>> > bdis...@dissensoftware.com>
:>> > :>wrote:
:>> > :>
:>> > :>> On Sun, 5 Jul 2020 11:31:55 -0500 Joe Monk
:>> 
:>> > wrote:
:>> > :>>
:>> > :>> :>Cobol has alignment too. You just dont see it.
:>> > :>>
:>> > :>> :>All storage is aligned.
:>> > :>>
:>> > :>> The opposite is true.
:>> > :>>
:>> > :>> Group (01/77) are aligned.
:>> > :>>
:>> > :>> Subordinate items are not aligned unless the SYNC clause is specified.
:>> > :>>
:>> > :>> :>On Sun, Jul 5, 2020 at 10:24 AM Nguyen Dt 
:>> wrote:
:>> > :>> :>
:>> > :>> :>> Thank you all for your inputs,
:>> > :>> :>>
:>> > :>> :>> I am over the problem now.
:>> > :>> :>> In fact what i tried to do is to Move some fields to my output
:>> > fields
:>> > :>> and
:>> > :>> :>> then write it as a report. (It is a Db2 performance report, the
:>> > input
:>> > :>> are
:>> > :>> :>> from the trace buffers with the macros given by Db2 libraries)
:>> > :>> :>>
:>> > :>> :>> So my program is roughly like this
:>> > :>> :>> READ Buffer on QW... variables
:>> > :>> :>>
:>> > :>> :>> MVC OW...,QW...
:>> > :>> :>>
:>> > :>> :>>
:>> > :>> :>> OW... are the output fields i defined it exactly as in the DSECT
:>> > got
:>> > :>> from
:>> > :>> :>> the macros.
:>> > :>> :>> As it is an output field, the position is important  (and it is
:>> > why i
:>> > :>> :>> detected a problem in the positions of my fields)
:>> > :>> :>> Its is OK now with OW... variables defined as characters CLx
:>> > :>> :>>
:>> > :>> :>> (PS: When i use NOALIGN , the program abends at execution ...)
:>> > :>> :>>
:>> > :>> :>> As i learn assembler "on the flight" , there is some important
:>> > things
:>> > :>> that
:>> > :>> :>> i don' t understand , such as the alignment  This is something
:>> > we
:>> > :>> don't
:>> > :>> :>> care in cobol , rexx  Can you tell me why assembler has the
:>> > :>> alignment
:>> > :>> :>> in words that are easy to understand and visualize in my little
:>> > head ?
:>> > :>> :>>
:>> > :>> :>> Thank you again.
:>> > :>> :>> Duc
:>> > :>> :>>
:>> > :>> :>>
:>> > -

Re: Assembler question

2020-07-05 Thread Gibney, Dave
Actually, it is. But,  BLA-2 below is still offset 3 bytes from BLA-RECORD 
because BLA-1 is only 3 bytes long

> -Original Message-
> From: IBM Mainframe Discussion List  On
> Behalf Of Joe Monk
> Sent: Sunday, July 05, 2020 4:38 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Assembler question
> 
> 01 BLA-RECORD.
> 05 BLA-RECORD PIC X(4).
> 05 BLA-RECOR2 REDEFINES BLA-RECORD PIC X(3).
> 
> The 01 is aligned.
> The 05 is aligned.
> The second 05 is not aligned.
> 
> Joe
> 
> 
> On Sun, Jul 5, 2020 at 6:27 PM Binyamin Dissen
> 
> wrote:
> 
> > 01   BLA-RECORD.
> >05   BLA-1  PIC X(3).
> >05   BLA-2  PIC S9(8) COMP.
> >
> > Do you truly wish to assert that BLA-2 is aligned?
> >
> > On Sun, 5 Jul 2020 17:45:37 -0500 Joe Monk 
> wrote:
> >
> > :>"Subordinate items are not aligned"
> > :>
> > :>yeah, no.
> > :>
> > :>If an 01 is aligned, then the subordinate 05 under the 01 is also
> > aligned.
> > :>It has to be this way because of REDEFINES. I cant REDEFINE an unaligned
> > :>item into an aligned item.
> > :>
> > :>77 are aligned because they are standalone, i.e. no grouping.
> > :>
> > :>Joe
> > :>
> > :>On Sun, Jul 5, 2020 at 12:07 PM Binyamin Dissen <
> > bdis...@dissensoftware.com>
> > :>wrote:
> > :>
> > :>> On Sun, 5 Jul 2020 11:31:55 -0500 Joe Monk
> 
> > wrote:
> > :>>
> > :>> :>Cobol has alignment too. You just dont see it.
> > :>>
> > :>> :>All storage is aligned.
> > :>>
> > :>> The opposite is true.
> > :>>
> > :>> Group (01/77) are aligned.
> > :>>
> > :>> Subordinate items are not aligned unless the SYNC clause is specified.
> > :>>
> > :>> :>On Sun, Jul 5, 2020 at 10:24 AM Nguyen Dt 
> wrote:
> > :>> :>
> > :>> :>> Thank you all for your inputs,
> > :>> :>>
> > :>> :>> I am over the problem now.
> > :>> :>> In fact what i tried to do is to Move some fields to my output
> > fields
> > :>> and
> > :>> :>> then write it as a report. (It is a Db2 performance report, the
> > input
> > :>> are
> > :>> :>> from the trace buffers with the macros given by Db2 libraries)
> > :>> :>>
> > :>> :>> So my program is roughly like this
> > :>> :>> READ Buffer on QW... variables
> > :>> :>>
> > :>> :>> MVC OW...,QW...
> > :>> :>>
> > :>> :>>
> > :>> :>> OW... are the output fields i defined it exactly as in the DSECT
> > got
> > :>> from
> > :>> :>> the macros.
> > :>> :>> As it is an output field, the position is important  (and it is
> > why i
> > :>> :>> detected a problem in the positions of my fields)
> > :>> :>> Its is OK now with OW... variables defined as characters CLx
> > :>> :>>
> > :>> :>> (PS: When i use NOALIGN , the program abends at execution ...)
> > :>> :>>
> > :>> :>> As i learn assembler "on the flight" , there is some important
> > things
> > :>> that
> > :>> :>> i don' t understand , such as the alignment  This is something
> > we
> > :>> don't
> > :>> :>> care in cobol , rexx  Can you tell me why assembler has the
> > :>> alignment
> > :>> :>> in words that are easy to understand and visualize in my little
> > head ?
> > :>> :>>
> > :>> :>> Thank you again.
> > :>> :>> Duc
> > :>> :>>
> > :>> :>>
> > --
> > :>> :>> For IBM-MAIN subscribe / signoff / archive access instructions,
> > :>> :>> send email to lists...@listserv.ua.edu with the message: INFO
> > IBM-MAIN
> > :>> :>>
> > :>> :>
> > :>>
> > :>--
> > :>> :>For IBM-MAIN subscribe / signoff / archive access instructions,
> > :>> :>send email to lists...@listserv.ua.edu with the message: INFO
> > IBM-MAIN
> > :>>
> > :>> --
> > :>> Binyamin Dissen 
&g

Re: Assembler question

2020-07-05 Thread Joe Monk
01 BLA-RECORD.
05 BLA-RECORD PIC X(4).
05 BLA-RECOR2 REDEFINES BLA-RECORD PIC X(3).

The 01 is aligned.
The 05 is aligned.
The second 05 is not aligned.

Joe


On Sun, Jul 5, 2020 at 6:27 PM Binyamin Dissen 
wrote:

> 01   BLA-RECORD.
>05   BLA-1  PIC X(3).
>05   BLA-2  PIC S9(8) COMP.
>
> Do you truly wish to assert that BLA-2 is aligned?
>
> On Sun, 5 Jul 2020 17:45:37 -0500 Joe Monk  wrote:
>
> :>"Subordinate items are not aligned"
> :>
> :>yeah, no.
> :>
> :>If an 01 is aligned, then the subordinate 05 under the 01 is also
> aligned.
> :>It has to be this way because of REDEFINES. I cant REDEFINE an unaligned
> :>item into an aligned item.
> :>
> :>77 are aligned because they are standalone, i.e. no grouping.
> :>
> :>Joe
> :>
> :>On Sun, Jul 5, 2020 at 12:07 PM Binyamin Dissen <
> bdis...@dissensoftware.com>
> :>wrote:
> :>
> :>> On Sun, 5 Jul 2020 11:31:55 -0500 Joe Monk 
> wrote:
> :>>
> :>> :>Cobol has alignment too. You just dont see it.
> :>>
> :>> :>All storage is aligned.
> :>>
> :>> The opposite is true.
> :>>
> :>> Group (01/77) are aligned.
> :>>
> :>> Subordinate items are not aligned unless the SYNC clause is specified.
> :>>
> :>> :>On Sun, Jul 5, 2020 at 10:24 AM Nguyen Dt  wrote:
> :>> :>
> :>> :>> Thank you all for your inputs,
> :>> :>>
> :>> :>> I am over the problem now.
> :>> :>> In fact what i tried to do is to Move some fields to my output
> fields
> :>> and
> :>> :>> then write it as a report. (It is a Db2 performance report, the
> input
> :>> are
> :>> :>> from the trace buffers with the macros given by Db2 libraries)
> :>> :>>
> :>> :>> So my program is roughly like this
> :>> :>> READ Buffer on QW... variables
> :>> :>>
> :>> :>> MVC OW...,QW...
> :>> :>>
> :>> :>>
> :>> :>> OW... are the output fields i defined it exactly as in the DSECT
> got
> :>> from
> :>> :>> the macros.
> :>> :>> As it is an output field, the position is important  (and it is
> why i
> :>> :>> detected a problem in the positions of my fields)
> :>> :>> Its is OK now with OW... variables defined as characters CLx
> :>> :>>
> :>> :>> (PS: When i use NOALIGN , the program abends at execution ...)
> :>> :>>
> :>> :>> As i learn assembler "on the flight" , there is some important
> things
> :>> that
> :>> :>> i don' t understand , such as the alignment  This is something
> we
> :>> don't
> :>> :>> care in cobol , rexx  Can you tell me why assembler has the
> :>> alignment
> :>> :>> in words that are easy to understand and visualize in my little
> head ?
> :>> :>>
> :>> :>> Thank you again.
> :>> :>> Duc
> :>> :>>
> :>> :>>
> --
> :>> :>> For IBM-MAIN subscribe / signoff / archive access instructions,
> :>> :>> send email to lists...@listserv.ua.edu with the message: INFO
> IBM-MAIN
> :>> :>>
> :>> :>
> :>>
> :>--
> :>> :>For IBM-MAIN subscribe / signoff / archive access instructions,
> :>> :>send email to lists...@listserv.ua.edu with the message: INFO
> IBM-MAIN
> :>>
> :>> --
> :>> Binyamin Dissen 
> :>> http://www.dissensoftware.com
> :>>
> :>> Director, Dissen Software, Bar & Grill - Israel
> :>>
> :>>
> :>> Should you use the mailblocks package and expect a response from me,
> :>> you should preauthorize the dissensoftware.com domain.
> :>>
> :>> I very rarely bother responding to challenge/response systems,
> :>> especially those from irresponsible companies.
> :>>
> :>> --
> :>> For IBM-MAIN subscribe / signoff / archive access instructions,
> :>> send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
> :>>
> :>
> :>--
> :>For IBM-MAIN subscribe / signoff / archive access instructions,
> :>send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
>
> --
> Binyamin Dissen 
> http://www.dissensoftware.com
>
> Director, Dissen Software, Bar & Grill - Israel
>
>
> Should you use the mailblocks package and expect a response from me,
> you should preauthorize the dissensoftware.com domain.
>
> I very rarely bother responding to challenge/response systems,
> especially those from irresponsible companies.
>
> --
> For IBM-MAIN subscribe / signoff / archive access instructions,
> send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
>

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Re: Assembler question

2020-07-05 Thread Binyamin Dissen
01   BLA-RECORD.
   05   BLA-1  PIC X(3).
   05   BLA-2  PIC S9(8) COMP.

Do you truly wish to assert that BLA-2 is aligned?

On Sun, 5 Jul 2020 17:45:37 -0500 Joe Monk  wrote:

:>"Subordinate items are not aligned"
:>
:>yeah, no.
:>
:>If an 01 is aligned, then the subordinate 05 under the 01 is also aligned.
:>It has to be this way because of REDEFINES. I cant REDEFINE an unaligned
:>item into an aligned item.
:>
:>77 are aligned because they are standalone, i.e. no grouping.
:>
:>Joe
:>
:>On Sun, Jul 5, 2020 at 12:07 PM Binyamin Dissen 
:>wrote:
:>
:>> On Sun, 5 Jul 2020 11:31:55 -0500 Joe Monk  wrote:
:>>
:>> :>Cobol has alignment too. You just dont see it.
:>>
:>> :>All storage is aligned.
:>>
:>> The opposite is true.
:>>
:>> Group (01/77) are aligned.
:>>
:>> Subordinate items are not aligned unless the SYNC clause is specified.
:>>
:>> :>On Sun, Jul 5, 2020 at 10:24 AM Nguyen Dt  wrote:
:>> :>
:>> :>> Thank you all for your inputs,
:>> :>>
:>> :>> I am over the problem now.
:>> :>> In fact what i tried to do is to Move some fields to my output fields
:>> and
:>> :>> then write it as a report. (It is a Db2 performance report, the input
:>> are
:>> :>> from the trace buffers with the macros given by Db2 libraries)
:>> :>>
:>> :>> So my program is roughly like this
:>> :>> READ Buffer on QW... variables
:>> :>>
:>> :>> MVC OW...,QW...
:>> :>>
:>> :>>
:>> :>> OW... are the output fields i defined it exactly as in the DSECT got
:>> from
:>> :>> the macros.
:>> :>> As it is an output field, the position is important  (and it is why i
:>> :>> detected a problem in the positions of my fields)
:>> :>> Its is OK now with OW... variables defined as characters CLx
:>> :>>
:>> :>> (PS: When i use NOALIGN , the program abends at execution ...)
:>> :>>
:>> :>> As i learn assembler "on the flight" , there is some important things
:>> that
:>> :>> i don' t understand , such as the alignment  This is something we
:>> don't
:>> :>> care in cobol , rexx  Can you tell me why assembler has the
:>> alignment
:>> :>> in words that are easy to understand and visualize in my little head ?
:>> :>>
:>> :>> Thank you again.
:>> :>> Duc
:>> :>>
:>> :>> --
:>> :>> For IBM-MAIN subscribe / signoff / archive access instructions,
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:>>
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:>>
:>>
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Re: Assembler question

2020-07-05 Thread Charles Mills
1. Thanks for allowing me to clarify. I did not for a second mean "the OP 
should use Rexx instead." I was just comparing the learning curve for the two 
languages. 

2. Interesting idea. IBM ships a program with the C compiler called EDCDSECT 
that maps a DSECT into a struct. That program and its problems is a thread of 
its own. But I like what you are suggesting: software that would somehow map a 
DSECT into a Rexx stem. Rexx as you say would seem to be poorly suited: Rexx 
does not really have "records" made up of "fields." When I have tried to be 
systematic about mapping a record to Rexx I have defined offsets and lengths so 
that I could code SOMEFIELD = SUBSTR(RECORD, SOMEFIELD_OFFSET, 
SOMEFIELD_LENGTH). It would be very cool if one could create a "DSECT 
converter" that would create a conversion map such that one could code for 
example 

CALL CONVERT InputJFCB, MYJFCB, JFCBconversionMap
Say "DSN =" MYJFCB.JFCBDSNM ", Member =" MYJFCB.JFCBELNM

A lot of thought required. Converting every field from a non-trivial DSECT 
would be a lot of overhead.

Charles


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Paul Gilmartin
Sent: Sunday, July 5, 2020 1:51 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler question

On Sat, 4 Jul 2020 15:28:44 -0700, Charles Mills wrote:

>I am not sure what you are trying to achieve in the big picture but assembler 
>is not something you can spend a short time on and expect to have something 
>that works.
>
>Rexx -- you could study it for 5 minutes and be able to write SAY "Hello 
>World" and you would have a working first program. Not so with assembler. 
>There are an awful lot of gotchas before you can get to first base, before 
>your first working program.
>
I largely concur.

But the OP's intent was to access fields in a control block.  Rexx
is poorly suited to the task.  I wonder if someone has attempted
to map from an Assembler SYSPRINT or ASMADATA to an
initialization of a Rexx compound symbol and a few functions to
access the fields, such as:

GETFIELD:
parse arg NAME FIELD
Work = substr( value( NAME.CONTENT, NAME.FIELD.OFFSET, NAME.FIELD.LENGTH ) )
interpret 'return c2'NAME.FIELD.TYPE'( Work )'

(Work (not) in progress; totally untested; suffers Use-Mention conflation.)

-- gil

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Re: Assembler question

2020-07-05 Thread Peter Relson
>STCK does not show such a restriction. 

It used to. Those of us with long-ago-enough knowledge remember that well. 


Regardless, if there is a chance of an operand crossing a cache-line 
boundary, it might be in your best (performance, not functional) interest 
to make sure that it doesn't (if you have such control). The easiest way 
of doing that for an 8-byte operand is usually to make it 
doubleword-aligned.

This applies not just to STCK/STCKF. 

Some operands, such as those for CDS and CSG must be doubleword-aligned.
Some operands must be quadword-aligned (e.g., CDSG, LPQ). For those if the 
operand is below 2G, you might need to avoid the default behavior of 
GETMAIN and STORAGE OBTAIN which is to obtain storage on a doubleword 
boundary (such as by using the STARTBDY keyword).

Peter Relson
z/OS Core Technology Design


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Re: Assembler question

2020-07-05 Thread Joe Monk
"Subordinate items are not aligned"

yeah, no.

If an 01 is aligned, then the subordinate 05 under the 01 is also aligned.
It has to be this way because of REDEFINES. I cant REDEFINE an unaligned
item into an aligned item.

77 are aligned because they are standalone, i.e. no grouping.

Joe

On Sun, Jul 5, 2020 at 12:07 PM Binyamin Dissen 
wrote:

> On Sun, 5 Jul 2020 11:31:55 -0500 Joe Monk  wrote:
>
> :>Cobol has alignment too. You just dont see it.
>
> :>All storage is aligned.
>
> The opposite is true.
>
> Group (01/77) are aligned.
>
> Subordinate items are not aligned unless the SYNC clause is specified.
>
> :>On Sun, Jul 5, 2020 at 10:24 AM Nguyen Dt  wrote:
> :>
> :>> Thank you all for your inputs,
> :>>
> :>> I am over the problem now.
> :>> In fact what i tried to do is to Move some fields to my output fields
> and
> :>> then write it as a report. (It is a Db2 performance report, the input
> are
> :>> from the trace buffers with the macros given by Db2 libraries)
> :>>
> :>> So my program is roughly like this
> :>> READ Buffer on QW... variables
> :>>
> :>> MVC OW...,QW...
> :>>
> :>>
> :>> OW... are the output fields i defined it exactly as in the DSECT got
> from
> :>> the macros.
> :>> As it is an output field, the position is important  (and it is why i
> :>> detected a problem in the positions of my fields)
> :>> Its is OK now with OW... variables defined as characters CLx
> :>>
> :>> (PS: When i use NOALIGN , the program abends at execution ...)
> :>>
> :>> As i learn assembler "on the flight" , there is some important things
> that
> :>> i don' t understand , such as the alignment  This is something we
> don't
> :>> care in cobol , rexx  Can you tell me why assembler has the
> alignment
> :>> in words that are easy to understand and visualize in my little head ?
> :>>
> :>> Thank you again.
> :>> Duc
> :>>
> :>> --
> :>> For IBM-MAIN subscribe / signoff / archive access instructions,
> :>> send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
> :>>
> :>
> :>--
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>
> --
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> http://www.dissensoftware.com
>
> Director, Dissen Software, Bar & Grill - Israel
>
>
> Should you use the mailblocks package and expect a response from me,
> you should preauthorize the dissensoftware.com domain.
>
> I very rarely bother responding to challenge/response systems,
> especially those from irresponsible companies.
>
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Re: Assembler question

2020-07-05 Thread Paul Gilmartin
On Sat, 4 Jul 2020 15:28:44 -0700, Charles Mills wrote:

>I am not sure what you are trying to achieve in the big picture but assembler 
>is not something you can spend a short time on and expect to have something 
>that works.
>
>Rexx -- you could study it for 5 minutes and be able to write SAY "Hello 
>World" and you would have a working first program. Not so with assembler. 
>There are an awful lot of gotchas before you can get to first base, before 
>your first working program.
>
I largely concur.

But the OP's intent was to access fields in a control block.  Rexx
is poorly suited to the task.  I wonder if someone has attempted
to map from an Assembler SYSPRINT or ASMADATA to an
initialization of a Rexx compound symbol and a few functions to
access the fields, such as:

GETFIELD:
parse arg NAME FIELD
Work = substr( value( NAME.CONTENT, NAME.FIELD.OFFSET, NAME.FIELD.LENGTH ) )
interpret 'return c2'NAME.FIELD.TYPE'( Work )'

(Work (not) in progress; totally untested; suffers Use-Mention conflation.)

-- gil

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Re: Assembler question

2020-07-05 Thread Paul Gilmartin
On Sat, 4 Jul 2020 15:11:54 -0500, Nguyen Dt wrote:

>I tried the option NOALIGN when assembling , and it is OK now.
>
>So it means that i should examine my  assembling listing to check if variables 
>are not separated by some bytes for the alignement ? 
>When i put all the variable to Character type i don't have any aligment ...
>In my case i see the problem because the output is not as expected , but i 
>guess that it can source of errors. 
> 
An explicit length indicator suppresses alignment, so you might
keep the intended use of fields clearee by using, e.g.:
 DSFL4  (unaligned fullword)
rather than:
 DSCL4  (used as if fullword)

But beware of "0" repition factor:
 DS0F   Aligned!  IIRC
 DS0C   Unaligned.
 DSFL0  ???
-- gil

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Re: Assembler question

2020-07-05 Thread Paul Gilmartin
On Sun, 5 Jul 2020 10:23:53 -0500, Nguyen Dt wrote:
>
>In fact what i tried to do is to Move some fields to my output fields and then 
>write it as a report. (It is a Db2 performance report, the input are from the 
>trace buffers with the macros given by Db2 libraries) 
>
>So my program is roughly like this 
>READ Buffer on QW... variables 
>
>MVC OW...,QW...
> 
If you need to use similar mappings for different storage areas,
"Labeled USING" instructions may be the most useful technique:

https://www.ibm.com/support/knowledgecenter/SSLTBW_2.1.0/com.ibm.zos.v2r1.asma400/labus.htm

-- gil

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Re: Assembler question

2020-07-05 Thread retired mainframer
The assembler reflects the architecture of the machine.  Originally, you could 
not load a 32-bit integer (called a full word) into a register from memory 
unless the address was properly aligned.  Attempting to do so would cause the 
instruction to terminate and a program check interrupt (specification 
exception) to occur.  There were similar alignment restrictions on halfword 
integers, single and doubleword floating point values, and address values.

Some things have changed in the ensuing 50+ years.  Some misalignments no 
longer cause an interrupt, merely a degradation in performance.  Some newer 
more complex instructions come with new different alignment requirements.

When you specify an operand with an implied length and alignment, the assembler 
will automatically add padding as necessary before the operand to insure the 
implied alignment.  That is why your original DS F was shifted two bytes to the 
right.  The assembler also provides a way to override this default behavior for 
individual operands.  You do this by specify the desired length.  If you had 
coded DS FL4, your operand would have abutted the previous halfword operand.  
Whether this would have produced the desired result when you executed your 
program is a different issue.

If you haven't done so already, you can download the Principles of Operation 
manual which discusses the hardware in considerable detail.

> -Original Message-
> From: IBM Mainframe Discussion List  On
> Behalf Of Nguyen Dt
> Sent: Sunday, July 05, 2020 8:24 AM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Assembler question
> 
> Thank you all for your inputs,
> 
> I am over the problem now.
> In fact what i tried to do is to Move some fields to my output fields and 
> then write it
> as a report. (It is a Db2 performance report, the input are from the trace 
> buffers with
> the macros given by Db2 libraries)
> 
> So my program is roughly like this
> READ Buffer on QW... variables
> 
> MVC OW...,QW...
> 
> 
> OW... are the output fields i defined it exactly as in the DSECT got from the 
> macros.
> As it is an output field, the position is important  (and it is why i 
> detected a problem in
> the positions of my fields)
> Its is OK now with OW... variables defined as characters CLx
> 
> (PS: When i use NOALIGN , the program abends at execution ...)
> 
> As i learn assembler "on the flight" , there is some important things that i 
> don' t
> understand , such as the alignment  This is something we don't care in 
> cobol , rexx
>  Can you tell me why assembler has the alignment in words that are easy to
> understand and visualize in my little head ?
> 
> Thank you again.
> Duc
> 
> --
> For IBM-MAIN subscribe / signoff / archive access instructions,
> send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN

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Re: Assembler question

2020-07-05 Thread Paul Gilmartin
On Sun, 5 Jul 2020 10:23:53 -0500, Nguyen Dt wrote:
>
>OW... are the output fields i defined it exactly as in the DSECT got from the 
>macros.
>As it is an output field, the position is important  (and it is why i detected 
>a problem in the positions of my fields)
>Its is OK now with OW... variables defined as characters CLx
>
>(PS: When i use NOALIGN , the program abends at execution ...) 
> 
I would say, then, that "the macros" are carelessly crafted.

But did you call the DSECT macros from MACLIB or transcribe the
code into your program?  I recommend the former.

-- gil

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Re: Assembler question

2020-07-05 Thread Rupert Reynolds
OW... are the output fields i defined it exactly as in the DSECT got from
the macros.

> As it is an output field, the position is important  (and it is why i
> detected a problem in the positions of my fields)
> Its is OK now with OW... variables defined as characters CLx
>

If it works, it works. Good news. But your code might be more robust if you
were able to use the macro to define storage in your program (CSECT), or
use it to define a DSECT which maps storage in your code.

If you are able to post the line defining the macro (the line after the
actual word 'MACRO') from the macro library here I could say more, but the
idea is "Don't re-invent the wheel". If someone has defined the report
already, re-use their work if you can.


>
> (PS: When i use NOALIGN , the program abends at execution ...)
>

Yes, you get that :-)  NOALIGN is not often used, because there is usually
a better way. You'd have to double check every alignment. Why make life
hard for yourself?

>
> As i learn assembler "on the flight" , there is some important things that
> i don' t understand , such as the alignment  This is something we don't
> care in cobol , rexx  Can you tell me why assembler has the alignment
> in words that are easy to understand and visualize in my little head ?
>
It's the way the hardware has worked for many years. It actually made the
hardware simpler, faster and less expensive if it didn't have to allow for
odd alignment, for example. Every instruction is aligned on a halfword and
for some instructions (L, ST etc.) the data had to be aligned as well. Even
if the hardware now allows odd alignment (I don't know--I am out of date),
I'd say it's usually good practice to align things right anyway.

As an example from my 31-bit experience, if you really need to load or
store a register at an address that might not be aligned, I would use ICM
and STCM instead. These two do (mostly) the same thing, but only the first
would be correct for R8 pointing to an odd address. This is from memory, so
please forgive any mistakes :-

 ICM  R1,B'',0(R8)   B'' mask stores all 4 bytes,
unaligned and sets CC
 L R1,0(,R8)
Same comment for these two:-
 STCM  R1,B'',0(R8)
 STR1,0(,R8)

Rupert

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Re: Assembler question

2020-07-05 Thread Binyamin Dissen
On Sun, 5 Jul 2020 11:31:55 -0500 Joe Monk  wrote:

:>Cobol has alignment too. You just dont see it.

:>All storage is aligned.

The opposite is true.

Group (01/77) are aligned.

Subordinate items are not aligned unless the SYNC clause is specified.

:>On Sun, Jul 5, 2020 at 10:24 AM Nguyen Dt  wrote:
:>
:>> Thank you all for your inputs,
:>>
:>> I am over the problem now.
:>> In fact what i tried to do is to Move some fields to my output fields and
:>> then write it as a report. (It is a Db2 performance report, the input are
:>> from the trace buffers with the macros given by Db2 libraries)
:>>
:>> So my program is roughly like this
:>> READ Buffer on QW... variables
:>>
:>> MVC OW...,QW...
:>>
:>>
:>> OW... are the output fields i defined it exactly as in the DSECT got from
:>> the macros.
:>> As it is an output field, the position is important  (and it is why i
:>> detected a problem in the positions of my fields)
:>> Its is OK now with OW... variables defined as characters CLx
:>>
:>> (PS: When i use NOALIGN , the program abends at execution ...)
:>>
:>> As i learn assembler "on the flight" , there is some important things that
:>> i don' t understand , such as the alignment  This is something we don't
:>> care in cobol , rexx  Can you tell me why assembler has the alignment
:>> in words that are easy to understand and visualize in my little head ?
:>>
:>> Thank you again.
:>> Duc
:>>
:>> --
:>> For IBM-MAIN subscribe / signoff / archive access instructions,
:>> send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
:>>
:>
:>--
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Director, Dissen Software, Bar & Grill - Israel


Should you use the mailblocks package and expect a response from me,
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Re: Assembler question

2020-07-05 Thread Joe Monk
Cobol has alignment too. You just dont see it.

All storage is aligned.

Joe

On Sun, Jul 5, 2020 at 10:24 AM Nguyen Dt  wrote:

> Thank you all for your inputs,
>
> I am over the problem now.
> In fact what i tried to do is to Move some fields to my output fields and
> then write it as a report. (It is a Db2 performance report, the input are
> from the trace buffers with the macros given by Db2 libraries)
>
> So my program is roughly like this
> READ Buffer on QW... variables
>
> MVC OW...,QW...
>
>
> OW... are the output fields i defined it exactly as in the DSECT got from
> the macros.
> As it is an output field, the position is important  (and it is why i
> detected a problem in the positions of my fields)
> Its is OK now with OW... variables defined as characters CLx
>
> (PS: When i use NOALIGN , the program abends at execution ...)
>
> As i learn assembler "on the flight" , there is some important things that
> i don' t understand , such as the alignment  This is something we don't
> care in cobol , rexx  Can you tell me why assembler has the alignment
> in words that are easy to understand and visualize in my little head ?
>
> Thank you again.
> Duc
>
> --
> For IBM-MAIN subscribe / signoff / archive access instructions,
> send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
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Re: Assembler question

2020-07-05 Thread DAL POS Raphael
Hi Duc,



You should have a look at Dr John  R.  Ehrman Assembler Programing Guide here :



http://www.cbttape.org/ftp/asmbook/alnv200.pdf



A must read if you want to learn z/OS Assembler.



Ciao,



--

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Generali Shared Services S.c.a.r.l.

GSS\CIN-MF (Central Infrastructure Mainframe)

11-17, Avenue François Mitterrand

93200 Saint Denis / France

Wilo W 03 B1 029C

raphael.dal...@generali.com +(33)1-58-38-59-67

  or mobile +(33)6.24.33.20.87

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-Message d'origine-
De : IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] De la part 
de Nguyen Dt
Envoyé : dimanche 5 juillet 2020 17:24
À : IBM-MAIN@LISTSERV.UA.EDU
Objet : Re: Assembler question



Thank you all for your inputs,



I am over the problem now.

In fact what i tried to do is to Move some fields to my output fields and then 
write it as a report. (It is a Db2 performance report, the input are from the 
trace buffers with the macros given by Db2 libraries)



So my program is roughly like this

READ Buffer on QW... variables



MVC OW...,QW...



OW... are the output fields i defined it exactly as in the DSECT got from the 
macros.

As it is an output field, the position is important  (and it is why i detected 
a problem in the positions of my fields)

Its is OK now with OW... variables defined as characters CLx



(PS: When i use NOALIGN , the program abends at execution ...)



As i learn assembler "on the flight" , there is some important things that i 
don' t understand , such as the alignment  This is something we don't care 
in cobol , rexx  Can you tell me why assembler has the alignment in words 
that are easy to understand and visualize in my little head ?



Thank you again.

Duc



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Re: Assembler question

2020-07-05 Thread Nguyen Dt
Thank you all for your inputs, 

I am over the problem now. 
In fact what i tried to do is to Move some fields to my output fields and then 
write it as a report. (It is a Db2 performance report, the input are from the 
trace buffers with the macros given by Db2 libraries) 

So my program is roughly like this 
READ Buffer on QW... variables 

MVC OW...,QW...
 

OW... are the output fields i defined it exactly as in the DSECT got from the 
macros.
As it is an output field, the position is important  (and it is why i detected 
a problem in the positions of my fields)
Its is OK now with OW... variables defined as characters CLx

(PS: When i use NOALIGN , the program abends at execution ...) 

As i learn assembler "on the flight" , there is some important things that i 
don' t understand , such as the alignment  This is something we don't care 
in cobol , rexx  Can you tell me why assembler has the alignment in words 
that are easy to understand and visualize in my little head ? 

Thank you again.
Duc

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Re: Assembler question

2020-07-04 Thread Seymour J Metz
> STCK does not show such a restriction.

You're correct. Neither does STCKE. Thanks.


--
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http://mason.gmu.edu/~smetz3


From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of 
Binyamin Dissen [bdis...@dissensoftware.com]
Sent: Saturday, July 4, 2020 8:20 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler question

Incorrect.

STCK does not show such a restriction.

On Sat, 4 Jul 2020 23:39:44 + Seymour J Metz  wrote:

:>> (Do CCWs still require doubleword alignment?  PSWs?  STCK?  CDS?)
:>
:>Yes.

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Re: Assembler question

2020-07-04 Thread Binyamin Dissen
Incorrect.

STCK does not show such a restriction.

On Sat, 4 Jul 2020 23:39:44 + Seymour J Metz  wrote:

:>> (Do CCWs still require doubleword alignment?  PSWs?  STCK?  CDS?)
:>
:>Yes.

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Re: Assembler question

2020-07-04 Thread Seymour J Metz
> Back in the olde daze, (not sure whether it is still true), loading a
> register from an address not aligned would cause an abend, or poor
> performance.

The change came with the byte oriented operand feature of the 360/85, and only 
applied to unprivileged instructions. If your code depended onnn getting a 
program interrupt with an IC of 6 then you had to rewrite it; there was no way 
to turn the feature off. AFAIK there is still a performance penalty, and there 
is also the issue of software that imposes its own alignment requirements.


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http://mason.gmu.edu/~smetz3


From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of 
Rupert Reynolds [rreyno...@cix.co.uk]
Sent: Saturday, July 4, 2020 5:34 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler question

The question on my mind is "What did you want to achieve?"

If you wanted an aligned fullword for OW0007AC then you need to decide
whether to align REPORT07 2 bytes after a fullword boundary (precede it
with CNOP 2,4 from memory) or whether you want slack bytes in the record.

Back in the olde daze, (not sure whether it is still true), loading a
register from an address not aligned would cause an abend, or poor
performance.

Rupert


On Sat., Jul. 4, 2020, 21:27 Joe Monk,  wrote:

> So in REPORT07, you have: 0CL274. This will not reserve any storage,
> because the multiplier is zero. (7FE).
>
> In the next variable, you have XL2. This is hex, length 2. Notice the
> location counter is at exactly the same place at REPORT07. (7FE).
>
> In the next variable you have XL2 again. This is hex, length 2. Notice the
> location counter has now increased by 2 (800).
>
> In the next variable, you have a Fullword. A fullword cannot start on a
> halfword boundary (802), so the assembler bumps the location counter to the
> next fullword (804).
>
> Same thing for your next two variables.
>
> Joe
>
> On Sat, Jul 4, 2020 at 2:48 PM Nguyen Dt  wrote:
>
> > Dear lister,
> > I am learning assembler on my own, i have something strange that i can't
> > explain , please help me to understand
> >
> > Here is a section of my code :
> >
> > 608 DBLWORD  DS  DDBLE WORD
> >
> > 609 PATTERN6 DC  X'402020202120'
> > 610 *
> >
> > 611 REPORTO7 DS  0CL274
> >
> > 612 OW0007DB DS  XL2
> >
> > 613 OW0007OB DS  XL2
> >
> > 614 OW0007AC DS  F
> >
> > 615 OW0007NP DS  H
> >
> > 616 OW0007PT DS  F
> >
> > 617 OW0007PF DS  CL256
> >
> > 618 *
> >
> >
> >
> > And here is the listing at compilation
> >
> > 0007FE  611 REPORTO7 DS  0CL274
> >
> > 0007FE  612 OW0007DB DS  XL2
> >
> > 000800  613 OW0007OB DS  XL2
> >
> > 000804  614 OW0007AC DS  F
> >
> > 000808  615 OW0007NP DS  H
> >
> > 00080C  616 OW0007PT DS  F
> >
> >
> >
> > I don't undestand why OW0007OB is 2 bytes  , but on the left it is
> > considered as 4 bytes long , the same for QW0007NP
> > I read something with alignment obut it seems to concern constants , and
> > this is not constant ?
> >
> >
> > Thank you for clarification
> >
> >
> > --
> > For IBM-MAIN subscribe / signoff / archive access instructions,
> > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
> >
>
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Re: Assembler question

2020-07-04 Thread Seymour J Metz
> (Do CCWs still require doubleword alignment?  PSWs?  STCK?  CDS?)

Yes.


--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3


From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of 
Paul Gilmartin [000433f07816-dmarc-requ...@listserv.ua.edu]
Sent: Saturday, July 4, 2020 6:25 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler question

On Sat, 4 Jul 2020 22:34:47 +0100, Rupert Reynolds wrote:

>The question on my mind is "What did you want to achieve?"
>
>If you wanted an aligned fullword for OW0007AC then you need to decide
>whether to align REPORT07 2 bytes after a fullword boundary (precede it
>with CNOP 2,4 from memory) or whether you want slack bytes in the record.
>
>Back in the olde daze, (not sure whether it is still true), loading a
>register from an address not aligned would cause an abend, or poor
>performance.
>
Perhaps still performance; mostly not ABEND.  (Do CCWs still require
doubleword alignment?  PSWs?  STCK?  CDS?)

If you have control of the placement, use the strategy automatic for
literals:  place the larger objects earlier.
-- gil

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Re: Assembler question

2020-07-04 Thread Charles Mills
I am not sure what you are trying to achieve in the big picture but assembler 
is not something you can spend a short time on and expect to have something 
that works.

Rexx -- you could study it for 5 minutes and be able to write SAY "Hello World" 
and you would have a working first program. Not so with assembler. There are an 
awful lot of gotchas before you can get to first base, before your first 
working program.

> it is OK now

One of the problems with getting going in assembler is that the assembler will 
let you do a lot of things that will not come close to running. If you write a 
simple COBOL program and get it to compile without errors there is a decent 
chance it might actually run successfully. Not so with assembler. I could write 
a bunch of utter machine code nonsense that would not have a prayer of running 
correctly and still it might assemble cleanly. So be very wary of thinking that 
no assembler errors means you have things correct.

Changing the subject slightly, for some reason

611 REPORTO7 DS  0CL274
612 OW0007DB DS  XL2
613 OW0007OB DS  XL2
614 OW0007AC DS  F

strikes me as disassembler output. Am I on the right track? Are you trying to 
assemble the output from a disassembler?

Charles


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Nguyen Dt
Sent: Saturday, July 4, 2020 1:12 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler question

I tried the option NOALIGN when assembling , and it is OK now.

So it means that i should examine my  assembling listing to check if variables 
are not separated by some bytes for the alignement ? 
When i put all the variable to Character type i don't have any aligment ...
In my case i see the problem because the output is not as expected , but i 
guess that it can source of errors. 

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Re: Assembler question

2020-07-04 Thread Paul Gilmartin
On Sat, 4 Jul 2020 22:34:47 +0100, Rupert Reynolds wrote:

>The question on my mind is "What did you want to achieve?"
>
>If you wanted an aligned fullword for OW0007AC then you need to decide
>whether to align REPORT07 2 bytes after a fullword boundary (precede it
>with CNOP 2,4 from memory) or whether you want slack bytes in the record.
>
>Back in the olde daze, (not sure whether it is still true), loading a
>register from an address not aligned would cause an abend, or poor
>performance.
> 
Perhaps still performance; mostly not ABEND.  (Do CCWs still require
doubleword alignment?  PSWs?  STCK?  CDS?)

If you have control of the placement, use the strategy automatic for
literals:  place the larger objects earlier.
-- gil

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Re: Assembler question

2020-07-04 Thread Mike Hochee
Hi Nguyen, 

In practice I don't think the NOALIGN option is used very frequently, probably 
because some instructions have alignment dependencies and will generate an 
error or warning when the instruction operand is not aligned as expected. There 
are undoubtedly exceptional cases where NOALIGN makes sense, but I would be 
inclined to stick with the default ALIGN behavior.

Also, Version 2.00 of Assembler Language Programming for IBM System z Servers, 
by John Ehrman, formerly of IBM but now sadly deceased, is a truly excellent 
guide and reference. Chapter 11 of this text relates to your question. 
Disappointingly, it appears that Marist College has relocated the document, but 
it still can be found here... (some other Marist location)  
http://148.100.100.35/enterprisesystemseducation/assemblerlanguageresources/Assembler.V2.alntext%20V2.00.pdf
  

Additional links for some of John Erhman's Assembler Bootcamp presentations on 
Assembler can be found here... 
https://share.confex.com/share/118/webprogram/Person3921.html 

HTH, 
Mike  

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Nguyen Dt
Sent: Saturday, July 4, 2020 4:12 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler question

Caution! This message was sent from outside your organization.

I tried the option NOALIGN when assembling , and it is OK now.

So it means that i should examine my  assembling listing to check if variables 
are not separated by some bytes for the alignement ?
When i put all the variable to Character type i don't have any aligment ...
In my case i see the problem because the output is not as expected , but i 
guess that it can source of errors.

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Re: Assembler question

2020-07-04 Thread David Betten
OW0007OB is only 2 bytes followed by 2 unused bytes.

The reason is that OQ0007AC is defines as a full word and thus has to be
full word aligned at address 000804.  If you had defined OW0007AC as just
XL4 it would've started at 000802.  Similarly, if you had defined it as D,
then it would have to be double word aligned and been located at 000808.




Have a nice day,
Dave Betten
z/OS Performance Specialist
Cloud and Systems Performance
IBM Corporation
email:  bet...@us.ibm.com


IBM Mainframe Discussion List  wrote on
07/04/2020 03:48:03 PM:

> From: Nguyen Dt 
> To: IBM-MAIN@LISTSERV.UA.EDU
> Date: 07/04/2020 03:48 PM
> Subject: [EXTERNAL] Assembler question
> Sent by: IBM Mainframe Discussion List 
>
> Dear lister,
> I am learning assembler on my own, i have something strange that i
> can't explain , please help me to understand
>
> Here is a section of my code :
>
> 608 DBLWORD  DS  DDBLE WORD
>
> 609 PATTERN6 DC  X'402020202120'
> 610 *
>
> 611 REPORTO7 DS  0CL274
>
> 612 OW0007DB DS  XL2
>
> 613 OW0007OB DS  XL2
>
> 614 OW0007AC DS  F
>
> 615 OW0007NP DS  H
>
> 616 OW0007PT DS  F
>
> 617 OW0007PF DS  CL256
>
> 618 *
>
>
>
> And here is the listing at compilation
>
> 0007FE  611 REPORTO7 DS  0CL274
>
> 0007FE  612 OW0007DB DS  XL2
>
> 000800  613 OW0007OB DS  XL2
>
> 000804  614 OW0007AC DS  F
>
> 000808  615 OW0007NP DS  H
>
> 00080C  616 OW0007PT DS  F
>
>
>
> I don't undestand why OW0007OB is 2 bytes  , but on the left it is
> considered as 4 bytes long , the same for QW0007NP
> I read something with alignment obut it seems to concern constants ,
> and this is not constant ?
>
>
> Thank you for clarification
>
>
> --
> For IBM-MAIN subscribe / signoff / archive access instructions,
> send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
>

--
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Re: Assembler question

2020-07-04 Thread Rupert Reynolds
The question on my mind is "What did you want to achieve?"

If you wanted an aligned fullword for OW0007AC then you need to decide
whether to align REPORT07 2 bytes after a fullword boundary (precede it
with CNOP 2,4 from memory) or whether you want slack bytes in the record.

Back in the olde daze, (not sure whether it is still true), loading a
register from an address not aligned would cause an abend, or poor
performance.

Rupert


On Sat., Jul. 4, 2020, 21:27 Joe Monk,  wrote:

> So in REPORT07, you have: 0CL274. This will not reserve any storage,
> because the multiplier is zero. (7FE).
>
> In the next variable, you have XL2. This is hex, length 2. Notice the
> location counter is at exactly the same place at REPORT07. (7FE).
>
> In the next variable you have XL2 again. This is hex, length 2. Notice the
> location counter has now increased by 2 (800).
>
> In the next variable, you have a Fullword. A fullword cannot start on a
> halfword boundary (802), so the assembler bumps the location counter to the
> next fullword (804).
>
> Same thing for your next two variables.
>
> Joe
>
> On Sat, Jul 4, 2020 at 2:48 PM Nguyen Dt  wrote:
>
> > Dear lister,
> > I am learning assembler on my own, i have something strange that i can't
> > explain , please help me to understand
> >
> > Here is a section of my code :
> >
> > 608 DBLWORD  DS  DDBLE WORD
> >
> > 609 PATTERN6 DC  X'402020202120'
> > 610 *
> >
> > 611 REPORTO7 DS  0CL274
> >
> > 612 OW0007DB DS  XL2
> >
> > 613 OW0007OB DS  XL2
> >
> > 614 OW0007AC DS  F
> >
> > 615 OW0007NP DS  H
> >
> > 616 OW0007PT DS  F
> >
> > 617 OW0007PF DS  CL256
> >
> > 618 *
> >
> >
> >
> > And here is the listing at compilation
> >
> > 0007FE  611 REPORTO7 DS  0CL274
> >
> > 0007FE  612 OW0007DB DS  XL2
> >
> > 000800  613 OW0007OB DS  XL2
> >
> > 000804  614 OW0007AC DS  F
> >
> > 000808  615 OW0007NP DS  H
> >
> > 00080C  616 OW0007PT DS  F
> >
> >
> >
> > I don't undestand why OW0007OB is 2 bytes  , but on the left it is
> > considered as 4 bytes long , the same for QW0007NP
> > I read something with alignment obut it seems to concern constants , and
> > this is not constant ?
> >
> >
> > Thank you for clarification
> >
> >
> > --
> > For IBM-MAIN subscribe / signoff / archive access instructions,
> > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
> >
>
> --
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>

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Re: Assembler question

2020-07-04 Thread Joe Monk
So in REPORT07, you have: 0CL274. This will not reserve any storage,
because the multiplier is zero. (7FE).

In the next variable, you have XL2. This is hex, length 2. Notice the
location counter is at exactly the same place at REPORT07. (7FE).

In the next variable you have XL2 again. This is hex, length 2. Notice the
location counter has now increased by 2 (800).

In the next variable, you have a Fullword. A fullword cannot start on a
halfword boundary (802), so the assembler bumps the location counter to the
next fullword (804).

Same thing for your next two variables.

Joe

On Sat, Jul 4, 2020 at 2:48 PM Nguyen Dt  wrote:

> Dear lister,
> I am learning assembler on my own, i have something strange that i can't
> explain , please help me to understand
>
> Here is a section of my code :
>
> 608 DBLWORD  DS  DDBLE WORD
>
> 609 PATTERN6 DC  X'402020202120'
> 610 *
>
> 611 REPORTO7 DS  0CL274
>
> 612 OW0007DB DS  XL2
>
> 613 OW0007OB DS  XL2
>
> 614 OW0007AC DS  F
>
> 615 OW0007NP DS  H
>
> 616 OW0007PT DS  F
>
> 617 OW0007PF DS  CL256
>
> 618 *
>
>
>
> And here is the listing at compilation
>
> 0007FE  611 REPORTO7 DS  0CL274
>
> 0007FE  612 OW0007DB DS  XL2
>
> 000800  613 OW0007OB DS  XL2
>
> 000804  614 OW0007AC DS  F
>
> 000808  615 OW0007NP DS  H
>
> 00080C  616 OW0007PT DS  F
>
>
>
> I don't undestand why OW0007OB is 2 bytes  , but on the left it is
> considered as 4 bytes long , the same for QW0007NP
> I read something with alignment obut it seems to concern constants , and
> this is not constant ?
>
>
> Thank you for clarification
>
>
> --
> For IBM-MAIN subscribe / signoff / archive access instructions,
> send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
>

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Re: Assembler question

2020-07-04 Thread Charles Mills
Right. It is two bytes. It occupies two bytes, 804 and 805. The assembler has 
then inserted two bytes of unused slack to that the following field -- defined 
as a fullword -- is fullword (multiple of four) aligned.

Charles


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Steve Austin
Sent: Saturday, July 4, 2020 12:57 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Assembler question

It is not 4 bytes, it is just that the following field is full word aligned. If 
the following field were FL4 rather than F, you will see the alignment change. 
I think there is an option to turn off alignment, but don't remember ever using 
it.

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Nguyen Dt
Sent: Saturday, July 4, 2020 8:48 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Assembler question

Dear lister,
I am learning assembler on my own, i have something strange that i can't 
explain , please help me to understand

Here is a section of my code :

608 DBLWORD  DS  DDBLE WORD

609 PATTERN6 DC  X'402020202120' 
610 *

611 REPORTO7 DS  0CL274

612 OW0007DB DS  XL2

613 OW0007OB DS  XL2

614 OW0007AC DS  F

615 OW0007NP DS  H

616 OW0007PT DS  F

617 OW0007PF DS  CL256

618 *



And here is the listing at compilation

0007FE  611 REPORTO7 DS  0CL274

0007FE  612 OW0007DB DS  XL2

000800  613 OW0007OB DS  XL2

000804  614 OW0007AC DS  F

000808  615 OW0007NP DS  H

00080C  616 OW0007PT DS  F

 

I don't undestand why OW0007OB is 2 bytes  , but on the left it is considered 
as 4 bytes long , the same for QW0007NP I read something with alignment obut it 
seems to concern constants , and this is not constant ? 


Thank you for clarification
 

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Re: Assembler question

2020-07-04 Thread Nguyen Dt
I tried the option NOALIGN when assembling , and it is OK now.

So it means that i should examine my  assembling listing to check if variables 
are not separated by some bytes for the alignement ? 
When i put all the variable to Character type i don't have any aligment ...
In my case i see the problem because the output is not as expected , but i 
guess that it can source of errors. 

--
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send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN


Re: Assembler question

2020-07-04 Thread Steve Austin
It is not 4 bytes, it is just that the following field is full word aligned. If 
the following field were FL4 rather than F, you will see the alignment change. 
I think there is an option to turn off alignment, but don't remember ever using 
it.

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Nguyen Dt
Sent: Saturday, July 4, 2020 8:48 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Assembler question

Dear lister,
I am learning assembler on my own, i have something strange that i can't 
explain , please help me to understand

Here is a section of my code :

608 DBLWORD  DS  DDBLE WORD

609 PATTERN6 DC  X'402020202120' 
610 *

611 REPORTO7 DS  0CL274

612 OW0007DB DS  XL2

613 OW0007OB DS  XL2

614 OW0007AC DS  F

615 OW0007NP DS  H

616 OW0007PT DS  F

617 OW0007PF DS  CL256

618 *



And here is the listing at compilation

0007FE  611 REPORTO7 DS  0CL274

0007FE  612 OW0007DB DS  XL2

000800  613 OW0007OB DS  XL2

000804  614 OW0007AC DS  F

000808  615 OW0007NP DS  H

00080C  616 OW0007PT DS  F

 

I don't undestand why OW0007OB is 2 bytes  , but on the left it is considered 
as 4 bytes long , the same for QW0007NP I read something with alignment obut it 
seems to concern constants , and this is not constant ? 


Thank you for clarification
 

--
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Assembler question

2020-07-04 Thread Nguyen Dt
Dear lister, 
I am learning assembler on my own, i have something strange that i can't 
explain , please help me to understand

Here is a section of my code :

608 DBLWORD  DS  DDBLE WORD

609 PATTERN6 DC  X'402020202120' 
610 *

611 REPORTO7 DS  0CL274

612 OW0007DB DS  XL2

613 OW0007OB DS  XL2

614 OW0007AC DS  F

615 OW0007NP DS  H

616 OW0007PT DS  F

617 OW0007PF DS  CL256

618 *



And here is the listing at compilation

0007FE  611 REPORTO7 DS  0CL274

0007FE  612 OW0007DB DS  XL2

000800  613 OW0007OB DS  XL2

000804  614 OW0007AC DS  F

000808  615 OW0007NP DS  H

00080C  616 OW0007PT DS  F

 

I don't undestand why OW0007OB is 2 bytes  , but on the left it is considered 
as 4 bytes long , the same for QW0007NP 
I read something with alignment obut it seems to concern constants , and this 
is not constant ? 


Thank you for clarification
 

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Re: Another elementary Assembler question

2017-07-04 Thread Charles Mills
Yes, the absence of an EXTRACT BEA instruction does seem like kind of an 
omission. The problem is you would need to be disabled for interrupts from 
before the break until the store. Otherwise "whose BEA are you getting?"

Right? I'm not missing something, am I? On a normal sort of S0C4, for example, 
there might be various task switches and such between *your* last branch and 
your S0C4, right? I don't live and breathe assembler dumps anymore. The BEA is 
only guaranteed to be useful in a wild branch situation, right? And *possibly* 
useful for other situations?

Yeah, I was stretching the concept of COMEFROM. I just got to riffing on the 
concept of a reverse branch table. Usually a branch table turns an index code 
into a branch-to address. This logic turns a branched-to address into an index 
code.

> Setting up an ESTAE and forcing a program check is probably just a bit

Plus of course the ESTAE setup would certainly involve a couple of breaking 
events of its own.

Charles


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Tony Harminc
Sent: Tuesday, July 4, 2017 9:41 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Another elementary Assembler question

On 3 July 2017 at 20:20, John McKown <john.archie.mck...@gmail.com> wrote:
> On Mon, Jul 3, 2017 at 6:35 PM, Charles Mills <charl...@mcn.org> wrote:
>> It's the elusive COMEFROM instruction. If most languages have a GOTO, 
>> why not a COEMFROM? This is a "where did I come from?" branch table.

I think it rather misses the spirit of the original FORTRAN COMEFROM...

> Sounds like an "ask the BEAR" question to me. (BEAR - Breaking Event Address 
> Register).

Except there is no Extract BEAR or similar machine instruction. (Well who knows 
what's in the millicode instruction set...) So you have to have an interrupt to 
see the BEAR, and it's not preserved anywhere unless there is an error 
condition. Setting up an ESTAE and forcing a program check is probably just a 
bit to discover the name you were invoked by..

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Re: Another elementary Assembler question

2017-07-04 Thread Tony Harminc
On 4 July 2017 at 12:40, Tony Harminc  wrote:
> Setting up an ESTAE and forcing a program check is probably just a bit to 
> discover the name you were
> invoked by..

"just a bit" -> "just a bit much"

Tony H.

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Re: Another elementary Assembler question

2017-07-04 Thread Tony Harminc
On 3 July 2017 at 20:20, John McKown  wrote:
> On Mon, Jul 3, 2017 at 6:35 PM, Charles Mills  wrote:
>> It's the elusive COMEFROM instruction. If most languages have a GOTO, why
>> not a COEMFROM? This is a "where did I come from?" branch table.

I think it rather misses the spirit of the original FORTRAN COMEFROM...

> Sounds like an "ask the BEAR" question to me. (BEAR - Breaking Event Address 
> Register).

Except there is no Extract BEAR or similar machine instruction. (Well
who knows what's in the millicode instruction set...) So you have to
have an interrupt to see the BEAR, and it's not preserved anywhere
unless there is an error condition. Setting up an ESTAE and forcing a
program check is probably just a bit to discover the name you were
invoked by..

Tony H.

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Re: Another elementary Assembler question

2017-07-04 Thread Mike Stayton
Another option is to used the CSVINFO service.  It is somewhat complicated to 
use.
https://www.ibm.com/support/knowledgecenter/SSLTBW_2.2.0/com.ibm.zos.v2r2.ieaa700/iea3a7_Description8.htm

The data are CSVMODI is described at:
https://www.ibm.com/support/knowledgecenter/SSLTBW_2.2.0/com.ibm.zos.v2r2.iead100/iead100532.htm
See the flag MODI_MINOR

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Re: Another elementary Assembler question

2017-07-03 Thread Charles Mills
There are two situations:

1. The alias points to exactly the same entry point as the primary.
2. The alias points to a different entry point than the primary.

(TTR may be the same in both cases? The physical load module is the same in 
both cases.)

There are two ways of answering the OP's question:

a. By chaining to the CDE and looking at the name of the entry point there.
b. With a "reverse branch table" or address comparison or similar.

(a.) works for both (1.) and (2.). 

(b.) works only with (2.)

Or, phrasing it the other way around: For (2.) you can use either (a.) or (b.). 
For (1.) you must use (a.).

Charles


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of CM Poncelet
Sent: Monday, July 3, 2017 5:47 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Another elementary Assembler question

An alias, in the PDS directory, points at the exact same 'CCTTR' (if memory 
serves) as the member that is aliased. So, from an LMOD's LP perspective, there 
is no distinguishable physical difference between loading an LMOD member or its 
alias.
 
Just my ha'penny.
 
Chris Poncelet (retired sysprog)
 


On 03/07/2017 14:49, PINION, RICHARD W. wrote:
> If I have an assembler program that has an alias, how can I determine 
> from within that program, what name was used to execute the program.
>
> SRC name = A
> Load module name = A
> Alias name= B
>
> Depending on how the program was executed A or B, I want the program to take 
> make certain decisions.
> FIRST TENNESSEE
>
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Re: Another elementary Assembler question

2017-07-03 Thread CM Poncelet
An alias, in the PDS directory, points at the exact same 'CCTTR' (if
memory serves) as the member that is aliased. So, from an LMOD's LP
perspective, there is no distinguishable physical difference between
loading an LMOD member or its alias.
 
Just my ha'penny.
 
Chris Poncelet (retired sysprog)
 


On 03/07/2017 14:49, PINION, RICHARD W. wrote:
> If I have an assembler program that has an alias, how can I determine from 
> within that program, what
> name was used to execute the program.
>
> SRC name = A
> Load module name = A
> Alias name= B
>
> Depending on how the program was executed A or B, I want the program to take 
> make certain decisions.
> FIRST TENNESSEE
>
> Confidentiality notice: 
> This e-mail message, including any attachments, may contain legally 
> privileged and/or confidential information. If you are not the intended 
> recipient(s), or the employee or agent responsible for delivery of this 
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> prohibited. If you have received this message in error, please immediately 
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Re: Another elementary Assembler question

2017-07-03 Thread John McKown
On Mon, Jul 3, 2017 at 6:35 PM, Charles Mills  wrote:

> It's kind of a reverse branch table.
>
> It's the elusive COMEFROM instruction. If most languages have a GOTO, why
> not a COEMFROM? This is a "where did I come from?" branch table.
>

​Sounds like an "ask the BEAR" question to me. (BEAR - Breaking Event
Address Register).​



>
> Charles
>
>

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Maranatha! <><
John McKown

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Re: Another elementary Assembler question

2017-07-03 Thread Charles Mills
It's kind of a reverse branch table.

It's the elusive COMEFROM instruction. If most languages have a GOTO, why not a 
COEMFROM? This is a "where did I come from?" branch table.

Charles


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of scott Ford
Sent: Monday, July 3, 2017 4:06 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Another elementary Assembler question

Charles,

Like a program branch table ?

Scott

On Mon, Jul 3, 2017 at 6:55 PM Charles Mills <charl...@mcn.org> wrote:

> I don't see the advantage of this approach, except that if you make it 
> SGR, AGHI and SGRL then it will work for AMODE 64 I think. Untested LOL.
>
> Charles
>
>
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] 
> On Behalf Of Hardee, Chuck
> Sent: Monday, July 3, 2017 3:10 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: *RE: Another elementary Assembler question
>
> Why not change your entry code slightly:
>
> WHATEVER CSECT
> ENTRY0   JAS   R15,MAIN
> ENTRY1   JAS   R15,MAIN
> ENTRY2   JAS   R15,MAIN
> ENTRY3   JAS   R15,MAIN
> ENTRY4   JAS   R15,MAIN
>  LARL  R12,WHATEVER
>  SRR15,R12  subtract r12 from R15 to get relative
> offset from WHATEVER
> *   R15 = 4 to 20 for entry 0 to 4
>  AHI   R15,-4   R15 = 0 to 16 for entry 0 to 4
>  SRL   R15,2R15 now has a code 0 to 4 corresponding to
> the entry point
>
> If you can live with 4 to 16 as your "code", then drop the AHI and 
> your
> R15 code will be 1 to 5.

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Re: Another elementary Assembler question

2017-07-03 Thread scott Ford
Charles,

Like a program branch table ?

Scott

On Mon, Jul 3, 2017 at 6:55 PM Charles Mills <charl...@mcn.org> wrote:

> I don't see the advantage of this approach, except that if you make it
> SGR, AGHI and SGRL then it will work for AMODE 64 I think. Untested LOL.
>
> Charles
>
>
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
> Behalf Of Hardee, Chuck
> Sent: Monday, July 3, 2017 3:10 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: *RE: Another elementary Assembler question
>
> Why not change your entry code slightly:
>
> WHATEVER CSECT
> ENTRY0   JAS   R15,MAIN
> ENTRY1   JAS   R15,MAIN
> ENTRY2   JAS   R15,MAIN
> ENTRY3   JAS   R15,MAIN
> ENTRY4   JAS   R15,MAIN
>  LARL  R12,WHATEVER
>  SRR15,R12  subtract r12 from R15 to get relative
> offset from WHATEVER
> *   R15 = 4 to 20 for entry 0 to 4
>  AHI   R15,-4   R15 = 0 to 16 for entry 0 to 4
>  SRL   R15,2R15 now has a code 0 to 4 corresponding to
> the entry point
>
> If you can live with 4 to 16 as your "code", then drop the AHI and your
> R15 code will be 1 to 5.
>
> --
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Re: Another elementary Assembler question

2017-07-03 Thread Charles Mills
I don't see the advantage of this approach, except that if you make it SGR, 
AGHI and SGRL then it will work for AMODE 64 I think. Untested LOL.

Charles


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Hardee, Chuck
Sent: Monday, July 3, 2017 3:10 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: *RE: Another elementary Assembler question

Why not change your entry code slightly:

WHATEVER CSECT
ENTRY0   JAS   R15,MAIN
ENTRY1   JAS   R15,MAIN
ENTRY2   JAS   R15,MAIN
ENTRY3   JAS   R15,MAIN
ENTRY4   JAS   R15,MAIN
 LARL  R12,WHATEVER
 SRR15,R12  subtract r12 from R15 to get relative offset 
from WHATEVER
*   R15 = 4 to 20 for entry 0 to 4
 AHI   R15,-4   R15 = 0 to 16 for entry 0 to 4
 SRL   R15,2R15 now has a code 0 to 4 corresponding to the 
entry point

If you can live with 4 to 16 as your "code", then drop the AHI and your R15 
code will be 1 to 5.

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Re: Another elementary Assembler question

2017-07-03 Thread Charles Mills
How can it not point to anything at all? I'm trying to wrap my brain around 
that concept. I know floating point has "not a number" -- does R15 contain "not 
an address"?

Seriously, yes, I knew that. I am assuming A/RMODE 24/31 below.

A more serious error is the lack of label MAIN, which should immediately 
precede the LARL.

Charles


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Steve Smith
Sent: Monday, July 3, 2017 2:56 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Another elementary Assembler question

If invoked with system services (LINK, EXEC, etc.) in AMODE 64, then R15 does 
not point to anything at all (S0C4-3? if you thought it did).

sas

On Mon, Jul 3, 2017 at 5:11 PM, Charles Mills <charl...@mcn.org> wrote:

> I have a program that has five (IIRC) entry points and sorts them out 
> that way.
>
> WHATEVER CSECT
> ENTRY0   J MAIN
> ENTRY1   J MAIN
> ENTRY2   J MAIN
> ENTRY3   J MAIN
> ENTRY4   J MAIN
>
>  LARL  R12,WHATEVER
>  USING WHATEVER,R12 Optional; irrelevant to this logic
>
>  SRR15,R12
>  SRL   R15,2R15 now has a code 0 to 4 corresponding to
> the entry point

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*RE: Another elementary Assembler question

2017-07-03 Thread Hardee, Chuck
Why not change your entry code slightly:

WHATEVER CSECT
ENTRY0   JAS   R15,MAIN
ENTRY1   JAS   R15,MAIN
ENTRY2   JAS   R15,MAIN
ENTRY3   JAS   R15,MAIN
ENTRY4   JAS   R15,MAIN
 LARL  R12,WHATEVER
 SRR15,R12  subtract r12 from R15 to get relative offset 
from WHATEVER
*   R15 = 4 to 20 for entry 0 to 4
 AHI   R15,-4   R15 = 0 to 16 for entry 0 to 4
 SRL   R15,2R15 now has a code 0 to 4 corresponding to the 
entry point

If you can live with 4 to 16 as your "code", then drop the AHI and your R15 
code will be 1 to 5.

C-

Charles (Chuck) Hardee
Senior Systems Engineer/Database Administration
EAS Information Technology

Thermo Fisher Scientific
300 Industry Drive | Pittsburgh, PA 15275
Phone +1 (724) 517-2633 | Mobile +1 (412) 877-2809 | FAX: +1 (412) 490-9230
chuck.har...@thermofisher.com  | www.thermofisher.com

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-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Steve Smith
Sent: Monday, July 03, 2017 4:56 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Another elementary Assembler question

If invoked with system services (LINK, EXEC, etc.) in AMODE 64, then R15
does not point to anything at all (S0C4-3? if you thought it did).

sas

On Mon, Jul 3, 2017 at 5:11 PM, Charles Mills <charl...@mcn.org> wrote:

> I have a program that has five (IIRC) entry points and sorts them out that
> way.
>
> WHATEVER CSECT
> ENTRY0   J MAIN
> ENTRY1   J MAIN
> ENTRY2   J MAIN
> ENTRY3   J MAIN
> ENTRY4   J MAIN
>
>  LARL  R12,WHATEVER
>  USING WHATEVER,R12 Optional; irrelevant to this logic
>
>  SRR15,R12
>  SRL   R15,2R15 now has a code 0 to 4 corresponding to
> the entry point
>
> Charles
>
>
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
> Behalf Of Webster, Chris
> Sent: Monday, July 3, 2017 1:33 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Another elementary Assembler question
>
> An alternative to looking up the cde.
>
>  Entry Alias1
> Alias1 J Main r15 points here for alias1 Entry Alias2
> Alias2 J Main r15 points here for alias2 Entry MAIN Main DS 0AD r15 points
> here for main  Larl 12,Main (or data area) set base  Using main,12  Larl
> 0,alias1 check for alias1
>  Cr15,0
>  Je...
>
> For amode 64, some cleanup of r15 would be needed.
>
> --
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Re: Another elementary Assembler question

2017-07-03 Thread Steve Smith
If invoked with system services (LINK, EXEC, etc.) in AMODE 64, then R15
does not point to anything at all (S0C4-3? if you thought it did).

sas

On Mon, Jul 3, 2017 at 5:11 PM, Charles Mills <charl...@mcn.org> wrote:

> I have a program that has five (IIRC) entry points and sorts them out that
> way.
>
> WHATEVER CSECT
> ENTRY0   J MAIN
> ENTRY1   J MAIN
> ENTRY2   J MAIN
> ENTRY3   J MAIN
> ENTRY4   J MAIN
>
>  LARL  R12,WHATEVER
>  USING WHATEVER,R12 Optional; irrelevant to this logic
>
>  SRR15,R12
>  SRL   R15,2R15 now has a code 0 to 4 corresponding to
> the entry point
>
> Charles
>
>
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
> Behalf Of Webster, Chris
> Sent: Monday, July 3, 2017 1:33 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Another elementary Assembler question
>
> An alternative to looking up the cde.
>
>  Entry Alias1
> Alias1 J Main r15 points here for alias1 Entry Alias2
> Alias2 J Main r15 points here for alias2 Entry MAIN Main DS 0AD r15 points
> here for main  Larl 12,Main (or data area) set base  Using main,12  Larl
> 0,alias1 check for alias1
>  Cr15,0
>  Je...
>
> For amode 64, some cleanup of r15 would be needed.
>
> --
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Re: Another elementary Assembler question

2017-07-03 Thread Charles Mills
I have a program that has five (IIRC) entry points and sorts them out that
way.

WHATEVER CSECT
ENTRY0   J MAIN
ENTRY1   J MAIN
ENTRY2   J MAIN 
ENTRY3   J MAIN 
ENTRY4   J MAIN 

 LARL  R12,WHATEVER
 USING WHATEVER,R12 Optional; irrelevant to this logic
   
 SRR15,R12
 SRL   R15,2R15 now has a code 0 to 4 corresponding to
the entry point

Charles


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of Webster, Chris
Sent: Monday, July 3, 2017 1:33 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Another elementary Assembler question

An alternative to looking up the cde.

 Entry Alias1
Alias1 J Main r15 points here for alias1 Entry Alias2
Alias2 J Main r15 points here for alias2 Entry MAIN Main DS 0AD r15 points
here for main  Larl 12,Main (or data area) set base  Using main,12  Larl
0,alias1 check for alias1
 Cr15,0
 Je...

For amode 64, some cleanup of r15 would be needed.

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Re: Another elementary Assembler question

2017-07-03 Thread Webster, Chris
An alternative to looking up the cde.

 Entry Alias1
Alias1 J Main r15 points here for alias1
Entry Alias2
Alias2 J Main r15 points here for alias2
Entry MAIN
Main DS 0AD r15 points here for main
 Larl 12,Main (or data area) set base
 Using main,12 
 Larl 0,alias1 check for alias1
 Cr15,0
 Je...

For amode 64, some cleanup of r15 would be needed.

...chris.

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Binyamin Dissen
Sent: July-03-17 7:31 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Another elementary Assembler question

Assuming EXEC PGM=, the CDE pointed to by the PRB will have the name.invoked.

On Mon, 3 Jul 2017 13:49:33 + "PINION, RICHARD W."
<rpin...@firsttennessee.com> wrote:

:>If I have an assembler program that has an alias, how can I determine from 
within that program, what :>name was used to execute the program.
:>
:>SRC name = A
:>Load module name = A
:>Alias name= B
:>
:>Depending on how the program was executed A or B, I want the program to take 
make certain decisions.
:>FIRST TENNESSEE
:>
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:>This e-mail message, including any attachments, may contain legally 
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Re: Another elementary Assembler question

2017-07-03 Thread Binyamin Dissen
Assuming EXEC PGM=, the CDE pointed to by the PRB will have the name.invoked.

On Mon, 3 Jul 2017 13:49:33 + "PINION, RICHARD W."
 wrote:

:>If I have an assembler program that has an alias, how can I determine from 
within that program, what
:>name was used to execute the program.
:>
:>SRC name = A
:>Load module name = A
:>Alias name= B
:>
:>Depending on how the program was executed A or B, I want the program to take 
make certain decisions.
:>FIRST TENNESSEE
:>
:>Confidentiality notice: 
:>This e-mail message, including any attachments, may contain legally 
privileged and/or confidential information. If you are not the intended 
recipient(s), or the employee or agent responsible for delivery of this message 
to the intended recipient(s), you are hereby notified that any dissemination, 
distribution, or copying of this e-mail message is strictly prohibited. If you 
have received this message in error, please immediately notify the sender and 
delete this e-mail message from your computer.
:>
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Re: Another elementary Assembler question

2017-07-03 Thread Dan @ Poodles
Simply add an entry point for the alias name and go from there.  We've done
this many times at EDS during the olden days.

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of PINION, RICHARD W.
Sent: Monday, July 3, 2017 8:50 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Another elementary Assembler question

If I have an assembler program that has an alias, how can I determine from
within that program, what name was used to execute the program.

SRC name = A
Load module name = A
Alias name= B

Depending on how the program was executed A or B, I want the program to take
make certain decisions.
FIRST TENNESSEE

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Re: Another elementary Assembler question

2017-07-03 Thread Charles Mills
This has been addressed here before. (Of course, it's not really an
assembler question -- would be a similar question if you coded in COBOL or
C.)

Probably the easiest thing is to give your program two distinct entry points
and note which one you came through.

There is control block chaining possible I believe to distinguish between
two named entry points both of which are the same address in the code, but I
do not recall it off hand.

Charles


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of PINION, RICHARD W.
Sent: Monday, July 3, 2017 6:50 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Another elementary Assembler question

If I have an assembler program that has an alias, how can I determine from
within that program, what name was used to execute the program.

SRC name = A
Load module name = A
Alias name= B

Depending on how the program was executed A or B, I want the program to take
make certain decisions.

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Another elementary Assembler question

2017-07-03 Thread PINION, RICHARD W.
If I have an assembler program that has an alias, how can I determine from 
within that program, what
name was used to execute the program.

SRC name = A
Load module name = A
Alias name= B

Depending on how the program was executed A or B, I want the program to take 
make certain decisions.
FIRST TENNESSEE

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and/or confidential information. If you are not the intended recipient(s), or 
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Re: Assembler question

2017-04-08 Thread Tony Thigpen

Thanks all. I got it working with MACRF=(GL,PL) and using PUTX.

Tony Thigpen

David W Noon wrote on 04/08/2017 11:20 AM:

On Fri, 7 Apr 2017 19:09:09 -0400, Tony Thigpen (t...@vse2pdf.com) wrote
about "Assembler question" (in <58e81c15.6060...@vse2pdf.com>):

[snip]

  OPEN  (HPPCTL,UPDAT)



HPPCTL   DCB   DSORG=PS,RECFM=F,LRECL=100,DDNAME=HPPCTL,
BLKSIZE=(100),
MACRF=(GM),EODAD=PPCTLOUT


You have specified UPDAT in your OPEN but your MACRF only has GM. If you
really are updating the dataset in place, you should have MACRF=(GL,PL),
or if you are only reading the dataset then your OPEN macro should
specify INPUT rather than UPDAT.

For either INPUT or UPDAT, you do not need to specify RECFM, LRECL or
BLKSIZE, as these will be taken from the format-1 DSCB. Specifying these
unnecessarily can corrupt the format-1, as the access method takes your
word for these values, not the existing ones in the format-1, so any
differences are put into the format-1 during the CLOSE macro -- at least
for UPDAT.

HTH



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Re: Assembler question

2017-04-08 Thread David W Noon
On Fri, 7 Apr 2017 19:09:09 -0400, Tony Thigpen (t...@vse2pdf.com) wrote
about "Assembler question" (in <58e81c15.6060...@vse2pdf.com>):

[snip]
>  OPEN  (HPPCTL,UPDAT)

> HPPCTL   DCB   DSORG=PS,RECFM=F,LRECL=100,DDNAME=HPPCTL,
>BLKSIZE=(100),
>MACRF=(GM),EODAD=PPCTLOUT

You have specified UPDAT in your OPEN but your MACRF only has GM. If you
really are updating the dataset in place, you should have MACRF=(GL,PL),
or if you are only reading the dataset then your OPEN macro should
specify INPUT rather than UPDAT.

For either INPUT or UPDAT, you do not need to specify RECFM, LRECL or
BLKSIZE, as these will be taken from the format-1 DSCB. Specifying these
unnecessarily can corrupt the format-1, as the access method takes your
word for these values, not the existing ones in the format-1, so any
differences are put into the format-1 during the CLOSE macro -- at least
for UPDAT.

HTH
-- 
Regards,

Dave  [RLU #314465]
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
david.w.n...@googlemail.com (David W Noon)
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

 

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Re: Assembler question

2017-04-08 Thread Peter Hunkeler

> OPEN for UPDAT might require the GET LOCATE instead of GET MOVE.


Yes. See the FM "DFSMS Macro Instructions for Data Sets"
UPDAT
Data set to be updated in place or, for BDAM, blocks are to be updated or 
added. If you specify UPDAT using QSAM, you must use locate mode.
Restriction: The UPDAT option is not allowed for compressed format data sets, 
or UNIX files, or for magnetic tapes, or with large block interface.



--
Peter Hunkeler





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Peter Hunkeler

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Re: Assembler question

2017-04-07 Thread CM Poncelet
If memory serves, OPEN  (HPPCTL,UPDAT) should be coded as OPEN
(HPPCTL,'UPDAT') - with quotes around UPDAT (or INPUT or OUTPUT).

On 08/04/2017 00:28, Sam Siegel wrote:
> OPEN for UPDAT might require the GET LOCATE instead of GET MOVE.
> 
> Try OPEN for INPUT and see if work area is populated.
> 
> On Fri, Apr 7, 2017 at 4:09 PM, Tony Thigpen  wrote:
>> I am helping on an assembler program that is accessing a sequential file in
>> move mode, yet the move is not happening. R1 points to valid data after the
>> GET, but the record area specified was not filled in. This application is
>> being ported from VSE to z/OS.
>>
>> Code snippets:
>>
>>  OPEN  (HPPCTL,UPDAT)
>>  GET   HPPCTL,PPCT
>> HPPCTL   DCB   DSORG=PS,RECFM=F,LRECL=100,DDNAME=HPPCTL,
>>BLKSIZE=(100),
>>MACRF=(GM),EODAD=PPCTLOUT
>>
>> in program storage:
>> PPCT DS0CL100  CONTROL RECORD
>> PPID DSCL5 RECORD IDENT
>> ... and more
>>
>>
>> Thoughts?
>>
>> (My expertise is in VSE, not z/OS application programming.)
>>
>> --
>> Tony Thigpen
>>
>> --
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Re: Assembler question

2017-04-07 Thread Sam Siegel
OPEN for UPDAT might require the GET LOCATE instead of GET MOVE.

Try OPEN for INPUT and see if work area is populated.

On Fri, Apr 7, 2017 at 4:09 PM, Tony Thigpen  wrote:
> I am helping on an assembler program that is accessing a sequential file in
> move mode, yet the move is not happening. R1 points to valid data after the
> GET, but the record area specified was not filled in. This application is
> being ported from VSE to z/OS.
>
> Code snippets:
>
>  OPEN  (HPPCTL,UPDAT)
>  GET   HPPCTL,PPCT
> HPPCTL   DCB   DSORG=PS,RECFM=F,LRECL=100,DDNAME=HPPCTL,
>BLKSIZE=(100),
>MACRF=(GM),EODAD=PPCTLOUT
>
> in program storage:
> PPCT DS0CL100  CONTROL RECORD
> PPID DSCL5 RECORD IDENT
> ... and more
>
>
> Thoughts?
>
> (My expertise is in VSE, not z/OS application programming.)
>
> --
> Tony Thigpen
>
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Assembler question

2017-04-07 Thread Tony Thigpen
I am helping on an assembler program that is accessing a sequential file 
in move mode, yet the move is not happening. R1 points to valid data 
after the GET, but the record area specified was not filled in. This 
application is being ported from VSE to z/OS.


Code snippets:

 OPEN  (HPPCTL,UPDAT)
 GET   HPPCTL,PPCT
HPPCTL   DCB   DSORG=PS,RECFM=F,LRECL=100,DDNAME=HPPCTL,
   BLKSIZE=(100),
   MACRF=(GM),EODAD=PPCTLOUT

in program storage:
PPCT DS0CL100  CONTROL RECORD
PPID DSCL5 RECORD IDENT
... and more


Thoughts?

(My expertise is in VSE, not z/OS application programming.)

--
Tony Thigpen

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Re: Simple assembler question

2016-06-24 Thread Phil Smith III
Thanks to all who replied; the use case is returning a 64-bit value to a C 
function, which LE does by putting the top half in R0 and the bottom half in 
R15. Which is weird but is how it’s done. So I don’t much care about the top 
halves, nor bit 0 of the 32-bit register, but thanks for the concerns there!

 

…phsiii


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Re: Simple assembler question

2016-06-24 Thread Tony Harminc
On 24 June 2016 at 18:50, Charles Mills  wrote:
> Umm, Tony, did you read Programming Note 1.? 

Only after I'd figured it out myself. Of course there's still a
tendency to think that it somehow costs more to rotate the bits all
the way around, and it'd be faster/cheaper to rotate them the
"shortest way" to their destination. Well. who knows - maybe on an
8008 or something it does. But as we know, modern machines don't work
the simplistic way they are described.

Tony H.

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Re: Simple assembler question

2016-06-24 Thread Steve Beaver
I have enjoyed this thread and gotten a good chuckle from Dave Cole

Steve  

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Charles Mills
Sent: Friday, June 24, 2016 3:39 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Simple assembler question

Sure. We were referring to the rotate instructions, the new whiz-bang 
instructions like RISBLGZ.

Charles

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Blaicher, Christopher Y.
Sent: Friday, June 24, 2016 1:24 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Simple assembler question

For the SLLG, SRLG, SRAG and others, if you load the B register with the number 
of bits to shift and set the D value to zero, you can shift a variable number 
of bits without using an EXECUTE instruction.

And there are SRL, SRDL, SRAG and SRLG that rotate right.

Chris Blaicher
Technical Architect
Mainframe Development
Syncsort Incorporated
50 Tice Boulevard, Woodcliff Lake, NJ 07677
P: 201-930-8234  |  M: 512-627-3803
E: cblaic...@syncsort.com

www.syncsort.com




-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Charles Mills
Sent: Friday, June 24, 2016 3:59 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Simple assembler question

> there are no versions of these instruction that rotate right...

Blatant liberal* slant?

Interesting. I was just looking at these instructions, which I have never used. 
The rotate count is an immediate operand, and not an immediate operand 
modifiable by Execute. Is there no way to rotate by an amount in a register, 
other than by modifying an instruction in storage, or with a loop?

For those like me who have trouble remembering the mapping between facilities 
and models, the high word facility comes along with the z196.

*Liberal in the American political sense, for our European and Asian members.

Charles

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Tony Harminc
Sent: Friday, June 24, 2016 12:15 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Simple assembler question

On 23 June 2016 at 17:51, Phil Smith III <li...@akphs.com> wrote:
>
> With all of the 273 new formats of LOAD, I assume this is hiding in there 
> somewhere:

> I have a value in grande register 3. I need the high-order bits in 
> 32-bit R0 and the low-order bits in 32-bit R15.

The RxSB... instructions are marvels in several ways, not least for having in 
some cases five operands, and in some cases 7-character names. And because 
there are some extended assembler mnemonics that bear no resemblance to the 
name or description of the base instruction.

RISBLG[Z] is Rotate then Insert Selected Bits Low [and Zero remaining bits].

There is an extended mnemonic LLHFR (presumably Load Low from High Fullword 
Register) that generates

RISBLGZ R1,R2,0,31,32

but even the RISBLGZ mnemonic is an extension of the base RISBLG that turns on 
the "Zero remaining bits" flag.

These are actually great instructions for all sorts of things, and are 
recommended for performance reasons in Kevin Shum's IBM z Systems Processor 
Optimization Primer. If there's a catch, it's that they require the High Word 
Facility. I must admit I spent an embarassing number of minutes wondering why 
there are no versions of these instruction that rotate right...

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Re: Simple assembler question

2016-06-24 Thread Frank Swarbrick
You ninja'd me!

> Date: Fri, 24 Jun 2016 15:50:53 -0700
> From: charl...@mcn.org
> Subject: Re: Simple assembler question
> To: IBM-MAIN@LISTSERV.UA.EDU
> 
> Umm, Tony, did you read Programming Note 1.? 
> 
> Charles
> 
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On 
> Behalf Of Tony Harminc
> Sent: Friday, June 24, 2016 2:54 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Simple assembler question
> 
> On 24 June 2016 at 16:23, Blaicher, Christopher Y.
> <cblaic...@syncsort.com> wrote:
> > And there are SRL, SRDL, SRAG and SRLG that rotate right.
> 
> Well, no, they *shift* right. There is no need for any instruction to rotate 
> right. As I said, I spent an embarassing amount of time pondering why IBM 
> provided only leftwards rotation, until the penny dropped. (I guess today 
> it's the pound that's dropped... :-(  )
> 
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Re: Simple assembler question

2016-06-24 Thread Charles Mills
Umm, Tony, did you read Programming Note 1.? 

Charles

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Tony Harminc
Sent: Friday, June 24, 2016 2:54 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Simple assembler question

On 24 June 2016 at 16:23, Blaicher, Christopher Y.
<cblaic...@syncsort.com> wrote:
> And there are SRL, SRDL, SRAG and SRLG that rotate right.

Well, no, they *shift* right. There is no need for any instruction to rotate 
right. As I said, I spent an embarassing amount of time pondering why IBM 
provided only leftwards rotation, until the penny dropped. (I guess today it's 
the pound that's dropped... :-(  )

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Re: Simple assembler question

2016-06-24 Thread Frank Swarbrick
Under ROTATE THEN INSERT SELECTED BITS the POP says:

1.  Although the bits 2-7 of the I5 field are defined to contain an unsigned 
binary integer specifying the number of bits that the second operand is rotated 
to the left, a negative value may be coded which effectively specifies a 
rotate-right amount.
> Date: Fri, 24 Jun 2016 17:54:26 -0400
> From: t...@harminc.net
> Subject: Re: Simple assembler question
> To: IBM-MAIN@LISTSERV.UA.EDU
> 
> On 24 June 2016 at 16:23, Blaicher, Christopher Y.
> <cblaic...@syncsort.com> wrote:
> > And there are SRL, SRDL, SRAG and SRLG that rotate right.
> 
> Well, no, they *shift* right. There is no need for any instruction to
> rotate right. As I said, I spent an embarassing amount of time
> pondering why IBM provided only leftwards rotation, until the penny
> dropped. (I guess today it's the pound that's dropped... :-(  )
> 
> Tony H.
> 
> --
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Re: Simple assembler question

2016-06-24 Thread Tony Harminc
On 24 June 2016 at 16:23, Blaicher, Christopher Y.
 wrote:
> And there are SRL, SRDL, SRAG and SRLG that rotate right.

Well, no, they *shift* right. There is no need for any instruction to
rotate right. As I said, I spent an embarassing amount of time
pondering why IBM provided only leftwards rotation, until the penny
dropped. (I guess today it's the pound that's dropped... :-(  )

Tony H.

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Re: Simple assembler question

2016-06-24 Thread Frank Swarbrick
I'm still waiting for the DWIMNWIS instruction.
> Date: Fri, 24 Jun 2016 15:15:08 -0400
> From: t...@harminc.net
> Subject: Re: Simple assembler question
> To: IBM-MAIN@LISTSERV.UA.EDU
> 
> On 23 June 2016 at 17:51, Phil Smith III <li...@akphs.com> wrote:
> >
> > With all of the 273 new formats of LOAD, I assume this is hiding in there 
> > somewhere:
> 
> > I have a value in grande register 3. I need the high-order bits in 32-bit R0
> > and the low-order bits in 32-bit R15.
> 
> The RxSB... instructions are marvels in several ways, not least for
> having in some cases five operands, and in some cases 7-character
> names. And because there are some extended assembler mnemonics that
> bear no resemblance to the name or description of the base
> instruction.
> 
> RISBLG[Z] is Rotate then Insert Selected Bits Low [and Zero remaining bits].
> 
> There is an extended mnemonic LLHFR (presumably Load Low from High
> Fullword Register) that generates
> 
> RISBLGZ R1,R2,0,31,32
> 
> but even the RISBLGZ mnemonic is an extension of the base RISBLG that
> turns on the "Zero remaining bits" flag.
> 
> These are actually great instructions for all sorts of things, and are
> recommended for performance reasons in Kevin Shum's IBM z Systems
> Processor Optimization Primer. If there's a catch, it's that they
> require the High Word Facility. I must admit I spent an embarassing
> number of minutes wondering why there are no versions of these
> instruction that rotate right...
> 
> Oh yes, so what I'm trying to say is that two variations on RISBxG[Z]
> would probably do just what you need.
> 
> Tony H.
> 
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Re: Simple assembler question

2016-06-24 Thread Charles Mills
Sure. We were referring to the rotate instructions, the new whiz-bang 
instructions like RISBLGZ.

Charles

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Blaicher, Christopher Y.
Sent: Friday, June 24, 2016 1:24 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Simple assembler question

For the SLLG, SRLG, SRAG and others, if you load the B register with the number 
of bits to shift and set the D value to zero, you can shift a variable number 
of bits without using an EXECUTE instruction.

And there are SRL, SRDL, SRAG and SRLG that rotate right.

Chris Blaicher
Technical Architect
Mainframe Development
Syncsort Incorporated
50 Tice Boulevard, Woodcliff Lake, NJ 07677
P: 201-930-8234  |  M: 512-627-3803
E: cblaic...@syncsort.com

www.syncsort.com




-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Charles Mills
Sent: Friday, June 24, 2016 3:59 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Simple assembler question

> there are no versions of these instruction that rotate right...

Blatant liberal* slant?

Interesting. I was just looking at these instructions, which I have never used. 
The rotate count is an immediate operand, and not an immediate operand 
modifiable by Execute. Is there no way to rotate by an amount in a register, 
other than by modifying an instruction in storage, or with a loop?

For those like me who have trouble remembering the mapping between facilities 
and models, the high word facility comes along with the z196.

*Liberal in the American political sense, for our European and Asian members.

Charles

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Tony Harminc
Sent: Friday, June 24, 2016 12:15 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Simple assembler question

On 23 June 2016 at 17:51, Phil Smith III <li...@akphs.com> wrote:
>
> With all of the 273 new formats of LOAD, I assume this is hiding in there 
> somewhere:

> I have a value in grande register 3. I need the high-order bits in 
> 32-bit R0 and the low-order bits in 32-bit R15.

The RxSB... instructions are marvels in several ways, not least for having in 
some cases five operands, and in some cases 7-character names. And because 
there are some extended assembler mnemonics that bear no resemblance to the 
name or description of the base instruction.

RISBLG[Z] is Rotate then Insert Selected Bits Low [and Zero remaining bits].

There is an extended mnemonic LLHFR (presumably Load Low from High Fullword 
Register) that generates

RISBLGZ R1,R2,0,31,32

but even the RISBLGZ mnemonic is an extension of the base RISBLG that turns on 
the "Zero remaining bits" flag.

These are actually great instructions for all sorts of things, and are 
recommended for performance reasons in Kevin Shum's IBM z Systems Processor 
Optimization Primer. If there's a catch, it's that they require the High Word 
Facility. I must admit I spent an embarassing number of minutes wondering why 
there are no versions of these instruction that rotate right...

--
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send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN


Re: Simple assembler question

2016-06-24 Thread Blaicher, Christopher Y.
For the SLLG, SRLG, SRAG and others, if you load the B register with the number 
of bits to shift and set the D value to zero, you can shift a variable number 
of bits without using an EXECUTE instruction.

And there are SRL, SRDL, SRAG and SRLG that rotate right.

Chris Blaicher
Technical Architect
Mainframe Development
Syncsort Incorporated
50 Tice Boulevard, Woodcliff Lake, NJ 07677
P: 201-930-8234  |  M: 512-627-3803
E: cblaic...@syncsort.com

www.syncsort.com




-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Charles Mills
Sent: Friday, June 24, 2016 3:59 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Simple assembler question

> there are no versions of these instruction that rotate right...

Blatant liberal* slant?

Interesting. I was just looking at these instructions, which I have never used. 
The rotate count is an immediate operand, and not an immediate operand 
modifiable by Execute. Is there no way to rotate by an amount in a register, 
other than by modifying an instruction in storage, or with a loop?

For those like me who have trouble remembering the mapping between facilities 
and models, the high word facility comes along with the z196.

*Liberal in the American political sense, for our European and Asian members.

Charles

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Tony Harminc
Sent: Friday, June 24, 2016 12:15 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Simple assembler question

On 23 June 2016 at 17:51, Phil Smith III <li...@akphs.com> wrote:
>
> With all of the 273 new formats of LOAD, I assume this is hiding in there 
> somewhere:

> I have a value in grande register 3. I need the high-order bits in
> 32-bit R0 and the low-order bits in 32-bit R15.

The RxSB... instructions are marvels in several ways, not least for having in 
some cases five operands, and in some cases 7-character names. And because 
there are some extended assembler mnemonics that bear no resemblance to the 
name or description of the base instruction.

RISBLG[Z] is Rotate then Insert Selected Bits Low [and Zero remaining bits].

There is an extended mnemonic LLHFR (presumably Load Low from High Fullword 
Register) that generates

RISBLGZ R1,R2,0,31,32

but even the RISBLGZ mnemonic is an extension of the base RISBLG that turns on 
the "Zero remaining bits" flag.

These are actually great instructions for all sorts of things, and are 
recommended for performance reasons in Kevin Shum's IBM z Systems Processor 
Optimization Primer. If there's a catch, it's that they require the High Word 
Facility. I must admit I spent an embarassing number of minutes wondering why 
there are no versions of these instruction that rotate right...

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Re: Simple assembler question

2016-06-24 Thread Charles Mills
> there are no versions of these instruction that rotate right...

Blatant liberal* slant?

Interesting. I was just looking at these instructions, which I have never used. 
The rotate count is an immediate operand, and not an immediate operand 
modifiable by Execute. Is there no way to rotate by an amount in a register, 
other than by modifying an instruction in storage, or with a loop?

For those like me who have trouble remembering the mapping between facilities 
and models, the high word facility comes along with the z196.

*Liberal in the American political sense, for our European and Asian members.

Charles

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Tony Harminc
Sent: Friday, June 24, 2016 12:15 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Simple assembler question

On 23 June 2016 at 17:51, Phil Smith III <li...@akphs.com> wrote:
>
> With all of the 273 new formats of LOAD, I assume this is hiding in there 
> somewhere:

> I have a value in grande register 3. I need the high-order bits in 
> 32-bit R0 and the low-order bits in 32-bit R15.

The RxSB... instructions are marvels in several ways, not least for having in 
some cases five operands, and in some cases 7-character names. And because 
there are some extended assembler mnemonics that bear no resemblance to the 
name or description of the base instruction.

RISBLG[Z] is Rotate then Insert Selected Bits Low [and Zero remaining bits].

There is an extended mnemonic LLHFR (presumably Load Low from High Fullword 
Register) that generates

RISBLGZ R1,R2,0,31,32

but even the RISBLGZ mnemonic is an extension of the base RISBLG that turns on 
the "Zero remaining bits" flag.

These are actually great instructions for all sorts of things, and are 
recommended for performance reasons in Kevin Shum's IBM z Systems Processor 
Optimization Primer. If there's a catch, it's that they require the High Word 
Facility. I must admit I spent an embarassing number of minutes wondering why 
there are no versions of these instruction that rotate right...

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Re: Simple assembler question

2016-06-24 Thread Tony Harminc
On 23 June 2016 at 17:51, Phil Smith III  wrote:
>
> With all of the 273 new formats of LOAD, I assume this is hiding in there 
> somewhere:

> I have a value in grande register 3. I need the high-order bits in 32-bit R0
> and the low-order bits in 32-bit R15.

The RxSB... instructions are marvels in several ways, not least for
having in some cases five operands, and in some cases 7-character
names. And because there are some extended assembler mnemonics that
bear no resemblance to the name or description of the base
instruction.

RISBLG[Z] is Rotate then Insert Selected Bits Low [and Zero remaining bits].

There is an extended mnemonic LLHFR (presumably Load Low from High
Fullword Register) that generates

RISBLGZ R1,R2,0,31,32

but even the RISBLGZ mnemonic is an extension of the base RISBLG that
turns on the "Zero remaining bits" flag.

These are actually great instructions for all sorts of things, and are
recommended for performance reasons in Kevin Shum's IBM z Systems
Processor Optimization Primer. If there's a catch, it's that they
require the High Word Facility. I must admit I spent an embarassing
number of minutes wondering why there are no versions of these
instruction that rotate right...

Oh yes, so what I'm trying to say is that two variations on RISBxG[Z]
would probably do just what you need.

Tony H.

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Re: Simple assembler question

2016-06-24 Thread Wayne Driscoll
Phil,
You may want to use LLGTR instead of LR, as LR will leave the high half of
R15 as it was, while LLGTR R15,R3 will zero the high 31 bits of R15 then
copy the low 31 bits from R3 into R15.
==
Wayne Driscoll
OMEGAMON DB2 L3 Support/Development
wdrisco(at)us(dot)ibm(dot)com
All opinions are mine, and do not represent
IBM Corporation.
==

IBM Mainframe Discussion List <IBM-MAIN@LISTSERV.UA.EDU> wrote on
06/23/2016 09:47:05 PM:

> From: Phil Smith III <li...@akphs.com>
> To: IBM-MAIN@LISTSERV.UA.EDU
> Date: 06/23/2016 09:47 PM
> Subject: Re: [IBM-MAIN] Simple assembler question
> Sent by: IBM Mainframe Discussion List <IBM-MAIN@LISTSERV.UA.EDU>
>
> Chuck wrote:
>
> >I would consider something like this:
>
> >LR  R15,R3  Copy low 32-bits to R15
>
> >SRLGR0,R3,32Copy upper 32-bits to R0
>
> >You may want to add an SR or XR for register 0 and 15 prior to the above
> two instructions if you want to make sure of the upper 32-bits of the
target
> registers.
>
>
>
> Thanks! I didn't know SRLG-that's some fancy instruction-and I'm
embarrassed
> to admit that the simple LR hadn't occurred to me. Hey, I've only been
> writing assembler since 1980.I was thinking there would be some new "copy
> the bottom half of a register" instruction-but of course that's what
> old-school LR does. Doh.
>
>
>
> .phsiii (not too embarrassed to admit when he's been dumb)
>
>
> --
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>

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Re: Simple assembler question

2016-06-24 Thread Peter Relson
>>LR  R15,R3  Copy low 32-bits to R15
>>SRLGR0,R3,32Copy upper 32-bits to R0

>You may want to add an SR or XR for register 0 and 15 prior to the 
>above two instructions if you want to make sure of the upper 
>32-bits of the target registers.

FWIW, you don't need to do anything to R0 prior to this because SRLG sets 
all 64 bits.
And of course you likely meant to do something to clear the high half of 
reg 15 (hence not SR, XR, in addition to instructions that are part of the 
high word facility introduced with z196, there are things like SGR, XGR, 
LGHI, LMH).

If there happens to be a requirement to preserve the high half of R0, SRLG 
into R0 by itself won't meet the needs.
 
Peter Relson
z/OS Core Technology Design


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Re: Simple assembler question

2016-06-24 Thread Tom Marchant
On Fri, 24 Jun 2016 00:23:18 -0500, Andre Schoeman wrote:

>SLLGR0,R3,32  /* Shift bits 0-31 in R3 to bits 32-63 in R0 */

I think you mean SRLG.

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Re: Simple assembler question

2016-06-24 Thread Tom Marchant
On Thu, 23 Jun 2016 22:27:37 +, Hardee, Chuck wrote:

>   LR  R15,R3  Copy low 32-bits to R15
>   SRLGR0,R3,32Copy upper 32-bits to R0
>
>You may want to add an SR or XR for register 0 and 15 prior to the above two 
>instructions if you want to make sure of the upper 32-bits of the target 
>registers.
>

The XR isn't necessary.
SRLG inserts zeroes in the high bits.
If you want the high 32 bits of R15 to be zeroes, use LLGFR.
Or, if you want the high 33 bits to be zeroes, use LLGTR.

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Re: Simple assembler question

2016-06-24 Thread Don Poitras
In article <9788957341066676.wa.adtschoemanyahoo...@listserv.ua.edu> you wrote:
> You forgot to specify whether the top 32 bits of R0 and R15 must be zero
> after the lower 32 bits have been manipulated.
> Assuming that you do, then:

> LLGFR   15,3 /* Load bits 32-63 in R3 into bits 32-63 of R15 and 
> clear bits 0-31 of R15 */
> XGR  0,0   /* Initialize 64-bit R0 to zero */
> SLLGR0,R3,32  /* Shift bits 0-31 in R3 to bits 32-63 in R0 */

> The original contents of R3 is preserved and the above can be
> executed in any AMODE

> Best regards, Andre

One caution. If the contents of the lower half of R3 are meant to 
be used to address memory below the bar, the contents of bit 32
need to be dealt with. In this case, LLGTR would be the correct
instruction. e.g.

LLGTR   15,3 /* Load bits 33-63 in R3 into bits 33-63 of R15 and clear 
bits 0-32 of R15 */

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Re: Simple assembler question

2016-06-23 Thread Andre Schoeman <adtschoe...@yahoo.ca>
You forgot to specify whether the top 32 bits of R0 and R15 must be zero
after the lower 32 bits have been manipulated.
Assuming that you do, then:

LLGFR   15,3 /* Load bits 32-63 in R3 into bits 32-63 of R15 and clear 
bits 0-31 of R15 */
XGR  0,0   /* Initialize 64-bit R0 to zero */
SLLGR0,R3,32  /* Shift bits 0-31 in R3 to bits 32-63 in R0 */

The original contents of R3 is preserved and the above can be
executed in any AMODE

Best regards, Andre

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Re: Simple assembler question

2016-06-23 Thread David Cole

Newbies!   ;-)






At 6/23/2016 10:47 PM, Phil Smith III wrote:

Chuck wrote:
>I would consider something like this:
>LR  R15,R3  Copy low 32-bits to R15
>SRLGR0,R3,32Copy upper 32-bits to R0
>You may want to add an SR or XR for register 0 and 15 prior to the above
two instructions if you want to make sure of the upper 32-bits of the target
registers.

Thanks! I didn't know SRLG-that's some fancy instruction-and I'm embarrassed
to admit that the simple LR hadn't occurred to me. Hey, I've only been
writing assembler since 1980.I was thinking there would be some new "copy
the bottom half of a register" instruction-but of course that's what
old-school LR does. Doh.

.phsiii (not too embarrassed to admit when he's been dumb)


Dave Cole
ColeSoft Marketing
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Re: Simple assembler question

2016-06-23 Thread Dave Cole

Newbies!   ;-)






At 6/23/2016 10:47 PM, Phil Smith III wrote:

Chuck wrote:
>I would consider something like this:
>LR  R15,R3  Copy low 32-bits to R15
>SRLGR0,R3,32Copy upper 32-bits to R0
>You may want to add an SR or XR for register 0 and 15 prior to the above
two instructions if you want to make sure of the upper 32-bits of the target
registers.

Thanks! I didn't know SRLG-that's some fancy instruction-and I'm embarrassed
to admit that the simple LR hadn't occurred to me. Hey, I've only been
writing assembler since 1980.I was thinking there would be some new "copy
the bottom half of a register" instruction-but of course that's what
old-school LR does. Doh.

.phsiii (not too embarrassed to admit when he's been dumb)


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Re: Simple assembler question

2016-06-23 Thread Phil Smith III
Chuck wrote:

>I would consider something like this:

>LR  R15,R3  Copy low 32-bits to R15

>SRLGR0,R3,32Copy upper 32-bits to R0

>You may want to add an SR or XR for register 0 and 15 prior to the above
two instructions if you want to make sure of the upper 32-bits of the target
registers.

 

Thanks! I didn't know SRLG-that's some fancy instruction-and I'm embarrassed
to admit that the simple LR hadn't occurred to me. Hey, I've only been
writing assembler since 1980.I was thinking there would be some new "copy
the bottom half of a register" instruction-but of course that's what
old-school LR does. Doh.

 

.phsiii (not too embarrassed to admit when he's been dumb)


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Re: Simple assembler question

2016-06-23 Thread Hardee, Chuck
Hi Phil,

I would consider something like this:

LR  R15,R3  Copy low 32-bits to R15
SRLGR0,R3,32Copy upper 32-bits to R0

You may want to add an SR or XR for register 0 and 15 prior to the above two 
instructions if you want to make sure of the upper 32-bits of the target 
registers.

Chuck

Charles (Chuck) Hardee
Senior Systems Engineer/Database Administration
EAS Information Technology

Thermo Fisher Scientific
300 Industry Drive | Pittsburgh, PA 15275
Phone +1 (724) 517-2633 | Mobile +1 (412) 877-2809 | FAX: +1 (412) 490-9230
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-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Phil Smith III
Sent: Thursday, June 23, 2016 5:51 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Simple assembler question

With all of the 273 new formats of LOAD, I assume this is hiding in there
somewhere:

 

I have a value in grande register 3. I need the high-order bits in 32-bit R0
and the low-order bits in 32-bit R15.

 

What's the simplest/fastest way to achieve this? I have no writable memory
available.

 

Thanks.

 

.phsiii (getting frustrated trying to read PofOp, though it's not the book's
fault!)

 


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Simple assembler question

2016-06-23 Thread Phil Smith III
With all of the 273 new formats of LOAD, I assume this is hiding in there
somewhere:

 

I have a value in grande register 3. I need the high-order bits in 32-bit R0
and the low-order bits in 32-bit R15.

 

What's the simplest/fastest way to achieve this? I have no writable memory
available.

 

Thanks.

 

.phsiii (getting frustrated trying to read PofOp, though it's not the book's
fault!)

 


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Re: C and Assembler question

2013-04-10 Thread Shmuel Metz (Seymour J.)
In 14a501ce346e$16790580$436b1080$@mcn.org, on 04/08/2013
   at 08:31 AM, Charles Mills charl...@mcn.org said:

No. Re-read MY code, not the OP's.

Okay. Yes, that does pass back the rc.

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Re: C and Assembler question

2013-04-08 Thread Shmuel Metz (Seymour J.)
In 135301ce33bf$5736eab0$05a4c010$@mcn.org, on 04/07/2013
   at 11:40 AM, Charles Mills charl...@mcn.org said:

No. Re-read my code.

No need; you save the STORAGE rc into a parameter, but that is not the
value in R15 when your code encounters EDCEPIL.

 STR15,0(R11) RETURN CODE, OK IF ZERO
   MODESET KEY=NZERO,MODE=PROB BACK TO MORTALITY
*-
   EDCEPIL

 
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Re: C and Assembler question

2013-04-08 Thread Charles Mills
No. Re-read MY code, not the OP's. Here

MODESET KEY=ZERO,MODE=SUP GO INTO SUPERVISOR MODE
STORAGE OBTAIN,LENGTH=(R9),SP=231,LOC=ANY
LRR3,R1
LRR5,R15
MODESET KEY=NZERO,MODE=PROB BACK TO MORTALITY
STR3,somewhere to pass back
*-
LRR15,R5  RC for caller
EDCEPIL

Charles

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of Shmuel Metz (Seymour J.)
Sent: Monday, April 08, 2013 7:30 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: C and Assembler question

In 135301ce33bf$5736eab0$05a4c010$@mcn.org, on 04/07/2013
   at 11:40 AM, Charles Mills charl...@mcn.org said:

No. Re-read my code.

No need; you save the STORAGE rc into a parameter, but that is not the value
in R15 when your code encounters EDCEPIL.

 STR15,0(R11) RETURN CODE, OK IF ZERO
   MODESET KEY=NZERO,MODE=PROB BACK TO MORTALITY
*-
   EDCEPIL

 
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Re: C and Assembler question

2013-04-07 Thread Shmuel Metz (Seymour J.)
In 123a01ce3301$c5d50920$517f1b60$@mcn.org, on 04/06/2013
   at 01:03 PM, Charles Mills charl...@mcn.org said:

 Are you sure?  Which rc is going to survive after
 rc = GETSP231(fullwd2,fullwd1,rc);

The one on the left of the equal sign! (Which is the value in R15
when you execute EDCEPIL.)

That would be the return code from the second MODESET, not the return
code from STORAGE.
 
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Re: C and Assembler question

2013-04-07 Thread Charles Mills
No. Re-read my code.

Charles

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of Shmuel Metz (Seymour J.)
Sent: Saturday, April 06, 2013 8:29 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: C and Assembler question

In 123a01ce3301$c5d50920$517f1b60$@mcn.org, on 04/06/2013
   at 01:03 PM, Charles Mills charl...@mcn.org said:

 Are you sure?  Which rc is going to survive after rc = 
 GETSP231(fullwd2,fullwd1,rc);

The one on the left of the equal sign! (Which is the value in R15 when 
you execute EDCEPIL.)

That would be the return code from the second MODESET, not the return code
from STORAGE.

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C and Assembler question

2013-04-06 Thread Scott Ford
Guys: 
I have an Assembler routine below i want to call in C. I have changed it to be 
LE conforming. 
GETSP231 START 0
GETSP231 AMODE 31
GETSP231 RMODE ANY
EDCPRLG BASEREG=R12,DSALEN=WORKLEN
USING LGINWORK,R13   SAVEAREA AND LOCAL VARS
*-
* LOADS STG AMOUNT  INTO R9, STG ADDR INTO R10 AND RC IN R11
*-
LMR9,R11,4(R1)   LOAD ADDRESS STG AMT, ADR  RC
L R9,0(R9)   STG AMT - S/B 4K MULTIPLE
MODESET KEY=ZERO,MODE=SUP GO INTO SUPERVISOR MODE
STORAGE OBTAIN,LENGTH=(9),SP=231,LOC=ANY
STR1,0(R5)   RETURN ADDR, IF ANY
STR15,0(R11) RETURN CODE, OK IF ZERO
MODESET KEY=NZERO,MODE=PROB BACK TO MORTALITY
*-
EDCEPIL
LTORG
LGINWORK EDCDSAD
WORKLEN  EQU   *-LGINWORK
YREGS
END   GETSP231 
In C is did this: 
/**/
#include stdio.h
#include string.h
#pragma linkage(GETSP231,OS)
int rc;
unsigned long int fullwd2;
char fullwd1[8];
main()
{
fullwd2 = 102400;
rc = GETSP231(fullwd2,fullwd1,rc);
printf(Getsp231 rc: %d\n,rc);
if (rc == 0 )
{ printf(Getsp231 allocation worked\n);
printf(Allocation of: %d\n,,fullwd2);
printf(Allocation at: %s\n,,fullwd1);
}
else
{ printf(Getsp231 allocation failed\n);
}
} 
I get a RC=0 which is great, but i should get the address passed back to C and 
I dont see it ..
So ...i call upon the great C crystal ball ... 
As always a big thanks,

Scott J Ford
Software Engineer
http://www.identityforge.com/

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Re: C and Assembler question

2013-04-06 Thread Gerhard Postpischil

On 4/6/2013 2:01 PM, Scott Ford wrote:

STR1,0(R5)   RETURN ADDR, IF ANY
I get a RC=0 which is great, but i should get the address passed back to C and 
I dont see it ..


As previously noted, you should store into R10, and preferably save the 
register values and do the stores after getting back to NZERO key.


Gerhard Postpischil
Bradford, Vermont

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Re: C and Assembler question

2013-04-06 Thread Bob Rutledge

Scott Ford wrote:
Guys: 
I have an Assembler routine below i want to call in C. I have changed it to be LE conforming. 
GETSP231 START 0

GETSP231 AMODE 31
GETSP231 RMODE ANY
EDCPRLG BASEREG=R12,DSALEN=WORKLEN
USING LGINWORK,R13   SAVEAREA AND LOCAL VARS
*-
* LOADS STG AMOUNT  INTO R9, STG ADDR INTO R10 AND RC IN R11
*-
LMR9,R11,4(R1)   LOAD ADDRESS STG AMT, ADR  RC
L R9,0(R9)   STG AMT - S/B 4K MULTIPLE
MODESET KEY=ZERO,MODE=SUP GO INTO SUPERVISOR MODE
STORAGE OBTAIN,LENGTH=(9),SP=231,LOC=ANY
STR1,0(R5)   RETURN ADDR, IF ANY
STR15,0(R11) RETURN CODE, OK IF ZERO
MODESET KEY=NZERO,MODE=PROB BACK TO MORTALITY
*-
EDCEPIL
LTORG
LGINWORK EDCDSAD
WORKLEN  EQU   *-LGINWORK
YREGS
END   GETSP231 
In C is did this: 
/**/

#include stdio.h
#include string.h
#pragma linkage(GETSP231,OS)
int rc;
unsigned long int fullwd2;
char fullwd1[8];
main()
{
fullwd2 = 102400;
rc = GETSP231(fullwd2,fullwd1,rc);
printf(Getsp231 rc: %d\n,rc);
if (rc == 0 )
{ printf(Getsp231 allocation worked\n);
printf(Allocation of: %d\n,,fullwd2);
printf(Allocation at: %s\n,,fullwd1);
}
else
{ printf(Getsp231 allocation failed\n);
}
} 
I get a RC=0 which is great


Are you sure?  Which rc is going to survive after

rc = GETSP231(fullwd2,fullwd1,rc);

Bob

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Re: C and Assembler question

2013-04-06 Thread Charles Mills
 Are you sure?  Which rc is going to survive after
 rc = GETSP231(fullwd2,fullwd1,rc);

The one on the left of the equal sign! (Which is the value in R15 when you
execute EDCEPIL.)

By far the easier one to deal with, IMHO. No worries about pass by
reference, no parameter counting, easy to deal with directly in a C if,
etc.

If it were I, I would 

MODESET KEY=ZERO,MODE=SUP GO INTO SUPERVISOR MODE
STORAGE OBTAIN,LENGTH=(R9),SP=231,LOC=ANY
LRR3,R1
LRR5,R15
MODESET KEY=NZERO,MODE=PROB BACK TO MORTALITY
STR3,somewhere to pass back
*-
LRR15,R5  RC for caller
EDCEPIL

I would also use more meaningful variable names than fullwdn.

Charles

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
Behalf Of Bob Rutledge
Sent: Saturday, April 06, 2013 12:28 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: C and Assembler question

Scott Ford wrote:
 Guys: 
 I have an Assembler routine below i want to call in C. I have changed it
to be LE conforming. 
...
 great

Are you sure?  Which rc is going to survive after

rc = GETSP231(fullwd2,fullwd1,rc);

Bob

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