Re: IARST64 in addrr

2019-03-14 Thread Steven Partlow
There are better designs than allocating storage at the explicit address in 
most cases (fork being the primary exception).

If it's the case that Kees mentioned of having a shared block that is allocated 
on first use (assuming you have good serialization), then use name tokens 
instead. A hard-coded address could fail if something changes in your system to 
make that address no longer accessible.

If you're browsing a lot of storage to display or search for something, then 
certainly don't allocate it which just wastes system resources and tells you 
nothing useful. This would be especially true for 64-bit storage that 
allocating and browsing large areas would end up backing a lot of memory than 
you'd really need.

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Re: IARST64 in addrr

2019-03-13 Thread Joseph Reichman
Thanks for the explanation 




> On Mar 13, 2019, at 3:16 PM, Jim Mulder  wrote:
> 
>  INADDR was added to STORAGE OBTAIN in SP4.3.0 to support
> FORKing in POSIX. POSIX did VSMLIST in the source space to 
> find out how storage is allocated, and then STORAGE OBTAINs 
> with INADDR in the target space to create the same storage
> allocations in the target.   At the time of the original 
> POSIX (OMVS) project, that was being done by separate 
> development team with a separate FMID, using what they could 
> of existing MVS services and doing the minimum of changes in 
> MVS itself. 
> 
>  By the time 64-bit virtual storage came along, 
> Unix System Services was integrated into the MVS BCP,
> and internal interface was created for  Unix System Services
> to ask RSM  to do the FORKing of memory objects.  So we have 
> had no need for an INADDR-like function for 64-bit storage. 
> 
> Jim Mulder z/OS Diagnosis, Design, Development, Test  IBM Corp. 
> Poughkeepsie NY
> 
>> From: "Joseph Reichman" 
>> To: IBM-MAIN@LISTSERV.UA.EDU
>> Date: 03/13/2019 03:00 PM
>> Subject: Re: IARST64 in addrr
>> Sent by: "IBM Mainframe Discussion List" 
>> 
>> Wonder why this functionality is not available above the bar
>> 
> 
> 
> 
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Re: IARST64 in addrr

2019-03-13 Thread Jim Mulder
  INADDR was added to STORAGE OBTAIN in SP4.3.0 to support
FORKing in POSIX. POSIX did VSMLIST in the source space to 
find out how storage is allocated, and then STORAGE OBTAINs 
with INADDR in the target space to create the same storage
allocations in the target.   At the time of the original 
POSIX (OMVS) project, that was being done by separate 
development team with a separate FMID, using what they could 
of existing MVS services and doing the minimum of changes in 
MVS itself. 

  By the time 64-bit virtual storage came along, 
Unix System Services was integrated into the MVS BCP,
and internal interface was created for  Unix System Services
to ask RSM  to do the FORKing of memory objects.  So we have 
had no need for an INADDR-like function for 64-bit storage. 
 
Jim Mulder z/OS Diagnosis, Design, Development, Test  IBM Corp. 
Poughkeepsie NY

> From: "Joseph Reichman" 
> To: IBM-MAIN@LISTSERV.UA.EDU
> Date: 03/13/2019 03:00 PM
> Subject: Re: IARST64 in addrr
> Sent by: "IBM Mainframe Discussion List" 
> 
> Wonder why this functionality is not available above the bar
> 



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Re: IARST64 in addrr

2019-03-13 Thread Seymour J Metz
PIC = Program Interrupt Code.


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From: IBM Mainframe Discussion List  on behalf of 
Elardus Engelbrecht 
Sent: Wednesday, March 13, 2019 2:32 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: IARST64 in addrr

Joseph Reichman wrote:

>I have been getting S0C4 pic 11 11 meaning not a translation error or a 
>invalid address but that it wasn’t allocated

What is 'pic 11 11'? Just like the other wizards, I am also confused by what 
you wrote.

Please post the full Abend message(s) and all the return and reason codes as 
well the register contents.

Groete / Greetings
Elardus Engelbrecht

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Re: IARST64 in addrr

2019-03-13 Thread Seymour J Metz
No, it means that the page table does not point to a valid page frame for that 
address. In no case is the page frame in core, since nothing in the z line uses 
core. It does not guarantee that the associated storage frame is not in RAM, 
since it may have been stolen but not yet used.


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From: IBM Mainframe Discussion List  on behalf of 
Mike Schwab 
Sent: Wednesday, March 13, 2019 6:44 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: IARST64 in addrr

PIC is Program Interuption Code.  Printed page 72 of
GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf  shows this to be
page translation error.  That means the logical page references is not
in CORE (RAM).  The operating system need to read in the logical
memory from paging files and retry the instruction.

On Wed, Mar 13, 2019 at 2:32 AM Binyamin Dissen
 wrote:
>
> Mr.  Joseph Reichman tends to think his code is super sekrit  and thus asks
> for help supplying minimum detail rather than simply providing the code so
> that we can figure it out.
>
> On Wed, 13 Mar 2019 06:45:32 + Anthony Thompson
>  wrote:
>
> :>I believe the OP is referring to the system trace table entries for a page 
> fault.
> :>
> :>Ant.
> :>
> :>-Original Message-
> :>From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On 
> Behalf Of Elardus Engelbrecht
> :>Sent: Wednesday, 13 March 2019 4:02 PM
> :>To: IBM-MAIN@LISTSERV.UA.EDU
> :>Subject: Re: IARST64 in addrr
> :>
> :>Joseph Reichman wrote:
> :>
> :>>I have been getting S0C4 pic 11 11 meaning not a translation error or a
> :>>invalid address but that it wasn’t allocated
> :>
> :>What is 'pic 11 11'? Just like the other wizards, I am also confused by 
> what you wrote.
> :>
> :>Please post the full Abend message(s) and all the return and reason codes 
> as well the register contents.
> :>
> :>Groete / Greetings
> :>Elardus Engelbrecht
>
> --
> Binyamin Dissen 
> http://secure-web.cisco.com/1bzuOtvaEmil4xf2WIgw3-N8wmQYLB0xU960jbQZAPOph0jWtW4n_MwFy25-MWOZ4_k70IxijpblJHTyLM4XyPgIs2LqxNQbM1QdrI4UqL1Cvh-JpmJLowk76P3uFQjtUbhHDS04YKJM_r0HkLhnzp-jrg4ILrauBIClb2qOZz6JMfZx33xnXLIrGQA52DNR6H066r9LMdbDEjQ2o0GgqEpNDIFn9VJdcSarxqbCyU-eSG8Yq8gSNRhpE61jKHZD_iRCpKqD7DYow5bgKbpmiSJmdu5tV7mWB1BFV23VImNvdO0Y3-eEV1O7fsOIXPJksT20iqgTjUQMnKWg-gmTMq5xBgYVGj6jYcsO3aGfwUQWvUbEiFXWeZ8mZXNDx4M_X/http%3A%2F%2Fwww.dissensoftware.com
>
> Director, Dissen Software, Bar & Grill - Israel
>
>
> Should you use the mailblocks package and expect a response from me,
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>
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> especially those from irresponsible companies.
>
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Re: IARST64 in addrr

2019-03-13 Thread Don Poitras
Because no one ever asked for it? In the scenario I described, using
IEANT* would work no matter where the control block was allocated.
If you have another use-case, you can submit an RFE.


In article <7ef29fbf-086a-4108-bfd4-bda2903ac...@gmail.com> you wrote:
> Wonder why this functionality is not available above the bar

> > On Mar 13, 2019, at 11:35 AM, Vernooij, Kees (ITOP NM) - KLM 
> >  wrote:
> > 
> > That makes sense, if you describe it differently:
> > We have a similar thing, we have a controlblock pointed from CVTUSER. If 
> > the pointer is not filled, the controlblock does not exist, so we getmain 
> > it and put its pointer in CVTUSER.
> > 
> > So then: "if the storage is not there" actually means: "if the pointer to 
> > the storage is not filled in".
> > 
> > Kees.
> > 
> > 
> >> -Original Message-
> >> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
> >> Behalf Of Don Poitras
> >> Sent: 13 March, 2019 16:16
> >> To: IBM-MAIN@LISTSERV.UA.EDU
> >> Subject: Re: IARST64 in addrr
> >> 
> >>> On Wed, 13 Mar 2019 09:29:56 -0400, Don Poitras wrote:
> >>>>> On Wed, 13 Mar 2019 08:00:14 -0400, Joseph Reichman wrote:
> >> User-Agent: tin/2.4.2-20171224 ("Lochhead") (UNIX) (NetBSD/7.1.2
> >> (amd64))
> >> 
> >> Again, I'm just guessing. If the storage isn't there and I obtain it,
> >> then I'm the first caller and I create the control block that subsequent
> >> callers will find.

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Re: IARST64 in addrr

2019-03-13 Thread Seymour J Metz
That's dangerous, but it's not my dog.


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http://mason.gmu.edu/~smetz3


From: IBM Mainframe Discussion List  on behalf of 
Vernooij, Kees (ITOP NM) - KLM 
Sent: Wednesday, March 13, 2019 11:35 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: IARST64 in addrr

That makes sense, if you describe it differently:
We have a similar thing, we have a controlblock pointed from CVTUSER. If the 
pointer is not filled, the controlblock does not exist, so we getmain it and 
put its pointer in CVTUSER.

So then: "if the storage is not there" actually means: "if the pointer to the 
storage is not filled in".

Kees.


> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
> Behalf Of Don Poitras
> Sent: 13 March, 2019 16:16
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: IARST64 in addrr
>
> > On Wed, 13 Mar 2019 09:29:56 -0400, Don Poitras wrote:
> > >> On Wed, 13 Mar 2019 08:00:14 -0400, Joseph Reichman wrote:
> User-Agent: tin/2.4.2-20171224 ("Lochhead") (UNIX) (NetBSD/7.1.2
> (amd64))
>
> Again, I'm just guessing. If the storage isn't there and I obtain it,
> then I'm the first caller and I create the control block that subsequent
> callers will find.
>
> --
> Don Poitras - SAS Development  -  SAS Institute Inc. - SAS Campus Drive
> sas...@sas.com   (919) 531-5637Cary, NC 27513
>
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Re: IARST64 in addrr

2019-03-13 Thread Joseph Reichman
Wonder why this functionality is not available above the bar



> On Mar 13, 2019, at 11:35 AM, Vernooij, Kees (ITOP NM) - KLM 
>  wrote:
> 
> That makes sense, if you describe it differently:
> We have a similar thing, we have a controlblock pointed from CVTUSER. If the 
> pointer is not filled, the controlblock does not exist, so we getmain it and 
> put its pointer in CVTUSER.
> 
> So then: "if the storage is not there" actually means: "if the pointer to the 
> storage is not filled in".
> 
> Kees.
> 
> 
>> -Original Message-
>> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
>> Behalf Of Don Poitras
>> Sent: 13 March, 2019 16:16
>> To: IBM-MAIN@LISTSERV.UA.EDU
>> Subject: Re: IARST64 in addrr
>> 
>>> On Wed, 13 Mar 2019 09:29:56 -0400, Don Poitras wrote:
>>>>> On Wed, 13 Mar 2019 08:00:14 -0400, Joseph Reichman wrote:
>> User-Agent: tin/2.4.2-20171224 ("Lochhead") (UNIX) (NetBSD/7.1.2
>> (amd64))
>> 
>> Again, I'm just guessing. If the storage isn't there and I obtain it,
>> then I'm the first caller and I create the control block that subsequent
>> callers will find.
>> 
>> --
>> Don Poitras - SAS Development  -  SAS Institute Inc. - SAS Campus Drive
>> sas...@sas.com   (919) 531-5637Cary, NC 27513
>> 
>> --
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Re: IARST64 in addrr

2019-03-13 Thread Vernooij, Kees (ITOP NM) - KLM
That makes sense, if you describe it differently:
We have a similar thing, we have a controlblock pointed from CVTUSER. If the 
pointer is not filled, the controlblock does not exist, so we getmain it and 
put its pointer in CVTUSER.

So then: "if the storage is not there" actually means: "if the pointer to the 
storage is not filled in".

Kees.


> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
> Behalf Of Don Poitras
> Sent: 13 March, 2019 16:16
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: IARST64 in addrr
> 
> > On Wed, 13 Mar 2019 09:29:56 -0400, Don Poitras wrote:
> > >> On Wed, 13 Mar 2019 08:00:14 -0400, Joseph Reichman wrote:
> User-Agent: tin/2.4.2-20171224 ("Lochhead") (UNIX) (NetBSD/7.1.2
> (amd64))
> 
> Again, I'm just guessing. If the storage isn't there and I obtain it,
> then I'm the first caller and I create the control block that subsequent
> callers will find.
> 
> --
> Don Poitras - SAS Development  -  SAS Institute Inc. - SAS Campus Drive
> sas...@sas.com   (919) 531-5637Cary, NC 27513
> 
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Re: IARST64 in addrr

2019-03-13 Thread Don Poitras
> On Wed, 13 Mar 2019 09:29:56 -0400, Don Poitras wrote:
> >> On Wed, 13 Mar 2019 08:00:14 -0400, Joseph Reichman wrote:
User-Agent: tin/2.4.2-20171224 ("Lochhead") (UNIX) (NetBSD/7.1.2 (amd64))

Again, I'm just guessing. If the storage isn't there and I obtain it,
then I'm the first caller and I create the control block that subsequent
callers will find.

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Re: IARST64 in addrr

2019-03-13 Thread Tom Marchant
On Wed, 13 Mar 2019 05:44:42 -0500, Mike Schwab wrote:

>PIC is Program Interuption Code.  Printed page 72 of
>GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf  shows this to be
>page translation error.  That means the logical page references is not
>in CORE (RAM).  The operating system need to read in the logical
>memory from paging files and retry the instruction.

Yes, PIC 11 is a page translation exception.
But a S0C4 with PIC 11 means that the storage has not been GETMAIN'ed.
There is nothing to page in.

-- 
Tom Marchant


>> :>Joseph Reichman wrote:
>> :>
>> :>>I have been getting S0C4 pic 11 11 meaning not a translation error or a
>> :>>invalid address but that it wasn’t allocated

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Re: IARST64 in addrr

2019-03-13 Thread Tom Marchant
On Wed, 13 Mar 2019 09:29:56 -0400, Don Poitras wrote:

>In article <9784938220113382.wa.m42tomibmmainyahoo@listserv.ua.edu> you 
>wrote:
>> On Wed, 13 Mar 2019 08:00:14 -0400, Joseph Reichman wrote:
>
>> >Please let me better explain I have a program
>> >That browses storage  I do VSMLOC to verify if the storage was allocated if 
>> >not I use STORAGE OBTAIN with inaddr parm I was wondering if/ why there was 
>> >wasn???t anything comparable in 64 bit mode
>> ROFL! That's the most ridiculous thing I have heard in a long time.
>> What do you think the point of that is?
>> --
>> Tom Marchant
>
>It sounds like the sort of thing people would do before name/token
>came along. It lets code bootstrap it's way to finding a common
>control block. I used to support code that used ENQ to do that.

Really?

You want to examine a location in virtual storage.

If that storage is not allocated in your address space, you use STORAGE OBTAIN 
to allocate storage at that address, so that you can examine it.

What would you hope to find at that location, having just obtained it?

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Re: IARST64 in addrr

2019-03-13 Thread Joseph Reichman
Thanks for your help will post tonite when I get home 

> On Mar 13, 2019, at 9:52 AM, Gord Tomlin  
> wrote:
> 
>> On 2019-03-13 08:00, Joseph Reichman wrote:
>> I have a program
>> That browses storage  I do VSMLOC to verify if the storage was allocated if 
>> not I use STORAGE OBTAIN with inaddr parm
> 
> So your program is browsing (virtual) storage, and if it encounters an 
> address that is not allocated it obtains storage so that there is something 
> to browse?
> 
> Help us to help you. Post code, and explain better what you are trying to 
> achieve.
> 
> --
> 
> Regards, Gord Tomlin
> Action Software International
> (a division of Mazda Computer Corporation)
> Tel: (905) 470-7113, Fax: (905) 470-6507
> Support: https://actionsoftware.com/support/
> 
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Re: IARST64 in addrr

2019-03-13 Thread Gord Tomlin

On 2019-03-13 08:00, Joseph Reichman wrote:

I have a program
That browses storage  I do VSMLOC to verify if the storage was allocated if not 
I use STORAGE OBTAIN with inaddr parm


So your program is browsing (virtual) storage, and if it encounters an 
address that is not allocated it obtains storage so that there is 
something to browse?


Help us to help you. Post code, and explain better what you are trying 
to achieve.


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Re: IARST64 in addrr

2019-03-13 Thread Don Poitras
In article <9784938220113382.wa.m42tomibmmainyahoo@listserv.ua.edu> you 
wrote:
> On Wed, 13 Mar 2019 08:00:14 -0400, Joseph Reichman wrote:

> >Please let me better explain I have a program 
> >That browses storage  I do VSMLOC to verify if the storage was allocated if 
> >not I use STORAGE OBTAIN with inaddr parm I was wondering if/ why there was 
> >wasn???t anything comparable in 64 bit mode  
> ROFL! That's the most ridiculous thing I have heard in a long time.
> What do you think the point of that is?
> -- 
> Tom Marchant

It sounds like the sort of thing people would do before name/token 
came along. It lets code bootstrap it's way to finding a common
control block. I used to support code that used ENQ to do that. 

-- 
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Re: IARST64 in addrr

2019-03-13 Thread Tom Marchant
On Wed, 13 Mar 2019 08:00:14 -0400, Joseph Reichman wrote:

>Please let me better explain I have a program 
>That browses storage  I do VSMLOC to verify if the storage was allocated if 
>not I use STORAGE OBTAIN with inaddr parm I was wondering if/ why there was 
>wasn’t anything comparable in 64 bit mode  


ROFL! That's the most ridiculous thing I have heard in a long time.

What do you think the point of that is?

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Re: IARST64 in addrr

2019-03-13 Thread Joseph Reichman
Please 

Please let me better explain I have a program 
That browses storage  I do VSMLOC to verify if the storage was allocated if not 
I use STORAGE OBTAIN with inaddr parm I was wondering if/ why there was wasn’t 
anything comparable in 64 bit mode  




> On Mar 13, 2019, at 6:44 AM, Mike Schwab  wrote:
> 
> PIC is Program Interuption Code.  Printed page 72 of
> GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf  shows this to be
> page translation error.  That means the logical page references is not
> in CORE (RAM).  The operating system need to read in the logical
> memory from paging files and retry the instruction.
> 
> On Wed, Mar 13, 2019 at 2:32 AM Binyamin Dissen
>  wrote:
>> 
>> Mr.  Joseph Reichman tends to think his code is super sekrit  and thus asks
>> for help supplying minimum detail rather than simply providing the code so
>> that we can figure it out.
>> 
>> On Wed, 13 Mar 2019 06:45:32 + Anthony Thompson
>>  wrote:
>> 
>> :>I believe the OP is referring to the system trace table entries for a page 
>> fault.
>> :>
>> :>Ant.
>> :>
>> :>-Original Message-
>> :>From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On 
>> Behalf Of Elardus Engelbrecht
>> :>Sent: Wednesday, 13 March 2019 4:02 PM
>> :>To: IBM-MAIN@LISTSERV.UA.EDU
>> :>Subject: Re: IARST64 in addrr
>> :>
>> :>Joseph Reichman wrote:
>> :>
>> :>>I have been getting S0C4 pic 11 11 meaning not a translation error or a
>> :>>invalid address but that it wasn’t allocated
>> :>
>> :>What is 'pic 11 11'? Just like the other wizards, I am also confused by 
>> what you wrote.
>> :>
>> :>Please post the full Abend message(s) and all the return and reason codes 
>> as well the register contents.
>> :>
>> :>Groete / Greetings
>> :>Elardus Engelbrecht
>> 
>> --
>> Binyamin Dissen 
>> http://www.dissensoftware.com
>> 
>> Director, Dissen Software, Bar & Grill - Israel
>> 
>> 
>> Should you use the mailblocks package and expect a response from me,
>> you should preauthorize the dissensoftware.com domain.
>> 
>> I very rarely bother responding to challenge/response systems,
>> especially those from irresponsible companies.
>> 
>> --
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>> send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
> 
> 
> 
> -- 
> Mike A Schwab, Springfield IL USA
> Where do Forest Rangers go to get away from it all?
> 
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Re: IARST64 in addrr

2019-03-13 Thread Elardus Engelbrecht
Mike Schwab wrote:

>PIC is Program Interuption Code.  Printed page 72 of 
>GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf  shows this to be page 
>translation error.  That means the logical page references is not in CORE 
>(RAM).  The operating system need to read in the logical memory from paging 
>files and retry the instruction.

Thanks. So I see that too in 'z/Architecture Principles of Operation' PDF 
bookie SA22-7832-11 (filename as downloaded from Big Blue is dz9zr011.pdf)

One snippet on page 6-32 (page 458 of 1902 pages) says:

"The page-translation exception is indicated by a program-interruption code of 
0011 hex".

I hope I quote the right snippet. I am wondering of the OP's 'page-invalid bit' 
is indeed one.

But still, if the OP wants full and free help, he should post what is needed. 
Dumps, Abend code + return/reason codes, full messages, etc. plus code snippets 
if needed.

Groete / Greetings
Elardus Engelbrecht

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Re: IARST64 in addrr

2019-03-13 Thread Mike Schwab
PIC is Program Interuption Code.  Printed page 72 of
GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf  shows this to be
page translation error.  That means the logical page references is not
in CORE (RAM).  The operating system need to read in the logical
memory from paging files and retry the instruction.

On Wed, Mar 13, 2019 at 2:32 AM Binyamin Dissen
 wrote:
>
> Mr.  Joseph Reichman tends to think his code is super sekrit  and thus asks
> for help supplying minimum detail rather than simply providing the code so
> that we can figure it out.
>
> On Wed, 13 Mar 2019 06:45:32 + Anthony Thompson
>  wrote:
>
> :>I believe the OP is referring to the system trace table entries for a page 
> fault.
> :>
> :>Ant.
> :>
> :>-Original Message-
> :>From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On 
> Behalf Of Elardus Engelbrecht
> :>Sent: Wednesday, 13 March 2019 4:02 PM
> :>To: IBM-MAIN@LISTSERV.UA.EDU
> :>Subject: Re: IARST64 in addrr
> :>
> :>Joseph Reichman wrote:
> :>
> :>>I have been getting S0C4 pic 11 11 meaning not a translation error or a
> :>>invalid address but that it wasn’t allocated
> :>
> :>What is 'pic 11 11'? Just like the other wizards, I am also confused by 
> what you wrote.
> :>
> :>Please post the full Abend message(s) and all the return and reason codes 
> as well the register contents.
> :>
> :>Groete / Greetings
> :>Elardus Engelbrecht
>
> --
> Binyamin Dissen 
> http://www.dissensoftware.com
>
> Director, Dissen Software, Bar & Grill - Israel
>
>
> Should you use the mailblocks package and expect a response from me,
> you should preauthorize the dissensoftware.com domain.
>
> I very rarely bother responding to challenge/response systems,
> especially those from irresponsible companies.
>
> --
> For IBM-MAIN subscribe / signoff / archive access instructions,
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Where do Forest Rangers go to get away from it all?

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Re: IARST64 in addrr

2019-03-13 Thread Binyamin Dissen
Mr.  Joseph Reichman tends to think his code is super sekrit  and thus asks
for help supplying minimum detail rather than simply providing the code so
that we can figure it out.

On Wed, 13 Mar 2019 06:45:32 + Anthony Thompson
 wrote:

:>I believe the OP is referring to the system trace table entries for a page 
fault.
:>
:>Ant.
:>
:>-Original Message-
:>From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On 
Behalf Of Elardus Engelbrecht
:>Sent: Wednesday, 13 March 2019 4:02 PM
:>To: IBM-MAIN@LISTSERV.UA.EDU
:>Subject: Re: IARST64 in addrr
:>
:>Joseph Reichman wrote:
:>
:>>I have been getting S0C4 pic 11 11 meaning not a translation error or a 
:>>invalid address but that it wasn’t allocated
:>
:>What is 'pic 11 11'? Just like the other wizards, I am also confused by what 
you wrote.
:>
:>Please post the full Abend message(s) and all the return and reason codes as 
well the register contents.
:>
:>Groete / Greetings
:>Elardus Engelbrecht

--
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http://www.dissensoftware.com

Director, Dissen Software, Bar & Grill - Israel


Should you use the mailblocks package and expect a response from me,
you should preauthorize the dissensoftware.com domain.

I very rarely bother responding to challenge/response systems,
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Re: IARST64 in addrr

2019-03-12 Thread Anthony Thompson
I believe the OP is referring to the system trace table entries for a page 
fault.

Ant.

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf 
Of Elardus Engelbrecht
Sent: Wednesday, 13 March 2019 4:02 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: IARST64 in addrr

Joseph Reichman wrote:

>I have been getting S0C4 pic 11 11 meaning not a translation error or a 
>invalid address but that it wasn’t allocated

What is 'pic 11 11'? Just like the other wizards, I am also confused by what 
you wrote.

Please post the full Abend message(s) and all the return and reason codes as 
well the register contents.

Groete / Greetings
Elardus Engelbrecht

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Re: IARST64 in addrr

2019-03-12 Thread Elardus Engelbrecht
Joseph Reichman wrote:

>I have been getting S0C4 pic 11 11 meaning not a translation error or a 
>invalid address but that it wasn’t allocated 

What is 'pic 11 11'? Just like the other wizards, I am also confused by what 
you wrote.

Please post the full Abend message(s) and all the return and reason codes as 
well the register contents.

Groete / Greetings
Elardus Engelbrecht

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Re: IARST64 in addrr

2019-03-12 Thread Peter Relson
The original question was not a question, but a statement with a question 
mark at the end. 
Presuming that the OP meant it as a question, I would answer "correct, it 
does not have it". Nor is there any reason it would or should.

>I have been getting S0C4 pic 11 11 meaning not a translation error or 
>a invalid address but that it wasn’t allocated 

I have no idea what a S0C4 pic 11 11 is. Assuming that the OP meant 
completion code S0C4 reason 11, that does always means translation error, 
and does always mean invalid address. A PIC 11 does not necessarily mean 
the latter, since it could be a resolvable page fault. 0C4-11 does not 
always mean not allocated but, if enabled (rather than disabled), it 
probably does always mean not allocated. 

How about the symptom dump or something that shows the time of error 
registers and PSW? 

If you want to know if a given 64-bit address is validly allocated that 
can be ascertained in IPCS and by some RSM services.

The only ULUT that I know of is not only not PI, it is OCO.  IBM will 
provide no information about this block or its usage or how to access it 
or what you might have done wrong trying to access it. As Rob Scott 
mentioned, there are interfaces available to extract informations about 
UCBs.

Peter Relson
z/OS Core Technology Design


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Re: IARST64 in addrr

2019-03-12 Thread Rob Scott
By "ULUT" do you mean the non-GUPI control block used by UCB services or 
something else?

If the former, why do you need to use it, instead of the supported APIs 
(UCBSCAN etc etc)?

Do you have the code section that is abending?

People on this list will generally try and help - but we are not clairvoyant.

Rob 

-Original Message-
From: IBM Mainframe Discussion List  On Behalf Of 
Joseph Reichman
Sent: Tuesday, March 12, 2019 10:40 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: IARST64 in addrr

I’m trying to access storage and not get a S0C4 let me be specfic the ulut is 
above bar I have been getting S0C4 pic 11 11 meaning not a translation error or 
a invalid address but that it wasn’t allocated 





> On Mar 12, 2019, at 6:35 PM, Rob Scott  wrote:
> 
> IARST64 returns the address of storage within a 64-bit cell pool whose cell 
> size is rounded up to the nearest power of 2 (max 65K).
> 
> Something like INADDR would not make sense, in my humble opinion.
> 
> As always, the question "what are you trying to achieve?" springs to mind.
> 
> Rob Scott
> Rocket Software
> 
> -Original Message-
> From: IBM Mainframe Discussion List  On 
> Behalf Of Joseph Reichman
> Sent: Tuesday, March 12, 2019 9:15 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: IARST64 in addrr
> 
> Hi
> 
> 
> 
> Storage has an option of specifying the address you would like to obtain with 
> INADDR the 64 bit mode IARST64 doesn't seem to have this ?
> 
> 
> 
> 
> 
> 
> 
> 
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Re: IARST64 in addrr

2019-03-12 Thread Joseph Reichman
I’m trying to access storage and not get a S0C4 let me be specfic the ulut is 
above bar
I have been getting S0C4 pic 11 11 meaning not a translation error or a invalid 
address but that it wasn’t allocated 





> On Mar 12, 2019, at 6:35 PM, Rob Scott  wrote:
> 
> IARST64 returns the address of storage within a 64-bit cell pool whose cell 
> size is rounded up to the nearest power of 2 (max 65K).
> 
> Something like INADDR would not make sense, in my humble opinion.
> 
> As always, the question "what are you trying to achieve?" springs to mind.
> 
> Rob Scott
> Rocket Software
> 
> -Original Message-
> From: IBM Mainframe Discussion List  On Behalf Of 
> Joseph Reichman
> Sent: Tuesday, March 12, 2019 9:15 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: IARST64 in addrr
> 
> Hi
> 
> 
> 
> Storage has an option of specifying the address you would like to obtain with 
> INADDR the 64 bit mode IARST64 doesn't seem to have this ?
> 
> 
> 
> 
> 
> 
> 
> 
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Re: IARST64 in addrr

2019-03-12 Thread Rob Scott
IARST64 returns the address of storage within a 64-bit cell pool whose cell 
size is rounded up to the nearest power of 2 (max 65K).

Something like INADDR would not make sense, in my humble opinion.

As always, the question "what are you trying to achieve?" springs to mind.

Rob Scott
Rocket Software

-Original Message-
From: IBM Mainframe Discussion List  On Behalf Of 
Joseph Reichman
Sent: Tuesday, March 12, 2019 9:15 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: IARST64 in addrr

Hi



Storage has an option of specifying the address you would like to obtain with 
INADDR the 64 bit mode IARST64 doesn't seem to have this ?








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IARST64 in addrr

2019-03-12 Thread Joseph Reichman
Hi

 

Storage has an option of specifying the address you would like to obtain
with INADDR the 64 bit mode IARST64 doesn't seem to have this ? 

 

 

 


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