Re: WEEDING OUT DSNS WITH CATALOG ENTRIES ONLY

2019-08-13 Thread John McKown
On Tue, Aug 13, 2019 at 9:37 AM esmie moo < 012780d99c7b-dmarc-requ...@listserv.ua.edu> wrote: > Gentle Readers, > Is there a way of weeding out dsns with cataloged entries only. I tried > DFDSS logical backup with NORUN option but it did not give me the desired > results. I coded the

Re: WEEDING OUT DSNS WITH CATALOG ENTRIES ONLY

2019-08-13 Thread ITschak Mugzach
If I recall correctly, the VTOC command (CBT) has an option to list datasets catalog status. Using volume masking you can achive need needs. ITschak On Tue, Aug 13, 2019 at 6:01 PM John McKown wrote: > On Tue, Aug 13, 2019 at 9:37 AM esmie moo < >

Re: Instruction speeds

2019-08-13 Thread Charles Mills
Noo That was what I was trying to say: you can no longer say "instruction X takes n cycles." You just cannot. That is why IBM no longer publishes such a thing. At best case an LR or an L take "no time at all" -- read what I wrote earlier. Worst case an LR takes a little while and an L

Re: Instruction speeds

2019-08-13 Thread Tony Harminc
On Tue, 13 Aug 2019 at 11:39, Steve Smith wrote: > There's a big difference between B- (base-index-displacement) branches and > J- (or BR-) (relative address) instructions. Surely by now, this should go > without saying. Regardless of whether they're "faster" or not, they are > much better,

Re: Instruction speeds

2019-08-13 Thread Jesse 1 Robinson
My advice is always to make it easy for next guy. Chances are, over time, the 'next guy' will be the future you. . . J.O.Skip Robinson Southern California Edison Company Electric Dragon Team Paddler SHARE MVS Program Co-Manager 323-715-0595 Mobile 626-543-6132 Office ⇐=== NEW robin...@sce.com

Re: NTP Server connectivity quandary

2019-08-13 Thread Mark Jacobs
That's what I think too. I've asked HW support to check it out. Mark Jacobs Sent from ProtonMail, Swiss-based encrypted email. GPG Public Key - https://api.protonmail.ch/pks/lookup?op=get=markjac...@protonmail.com ‐‐‐ Original Message ‐‐‐ On Tuesday, August 13, 2019 12:39 PM, Dana

Re: Instruction speeds

2019-08-13 Thread Rick J. Valles
Here’s my IEFBR15 “Utility” - it’s pretty fast: Active Usings: None Loc Object CodeAddr1 Addr2 Stmt Source Statement 000 2 1 IEFBR15 CSECT 00 07FF 2 BR15 3 END

Re: Instruction speeds

2019-08-13 Thread Seymour J Metz
Even on a S/360 some of the timing formulae were pretty hairy, and it got worse on the S/370. I shuuder to think of the size of a timing manual for a contemporary processor. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe

Re: [SUSPECTED SPAM] Re: Instruction speeds

2019-08-13 Thread Brian Chapman
Mike, I believe the difference is related to the fact that branch instructions require a base register and jump does not. Thank you, Brian Chapman On Tue, Aug 13, 2019 at 10:40 AM Mike Shaw wrote: > On 8/12/2019 9:33 PM, Christopher Y. Blaicher wrote: > > ..> > > JUMPs are faster than

Re: Instruction speeds

2019-08-13 Thread Charles Mills
+1 Hardware is cheap. Programmers (and bugs!) are expensive. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Giliad Wilf Sent: Tuesday, August 13, 2019 8:30 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: Instruction speeds

Re: Instruction speeds

2019-08-13 Thread Steve Smith
Write good code and forget about instruction timings. With any luck your code will have to perform on several generations of architecture and machines. There's a big difference between B- (base-index-displacement) branches and J- (or BR-) (relative address) instructions. Surely by now, this

Re: Instruction speeds

2019-08-13 Thread Charles Mills
> how do I know that my literal pool is actively > cached at execution of a certain instruction? Short answer: you cannot. Long answer: Keep your data in a 256-byte-aligned area separate from your instructions. If you are really fussy, separate read-only from read/write data in separate

Re: Instruction speeds

2019-08-13 Thread Charles Mills
A GREAT introduction to this topic, by someone who unlike me actually knows what he is talking about: https://linuxmain.blogspot.com/2017/02/zoptimizationprimer.html Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Brian

Re: Instruction speeds

2019-08-13 Thread Seymour J Metz
Avoid processor-specific optimizations; what is millicode on one box may not be on another. Worry first about getting your code correct and maintainable. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion List on

Re: ISPF Question - browsing variable length records

2019-08-13 Thread Paul Gilmartin
On Tue, 13 Aug 2019 17:39:09 +, Seymour J Metz wrote: >> Why not? The host should transmit characters counted by the RDW, then NULs >> to the end >> of the field. Characters typed over those NULs would be returned to the >> host on Read >> Modified; the NULs ignored. > >Yes, ignored, not

Re: Instruction speeds

2019-08-13 Thread Brian Chapman
Thanks Giliad. This is what I was searching for. I understand that the timings in this document are very old and probably wildly inaccurate for today's Z systems, but would it be on a relative scale? Would a LR be twice the speed of a L? Thank you, Brian Chapman On Tue, Aug 13, 2019 at 10:28

Re: WEEDING OUT DSNS WITH CATALOG ENTRIES ONLY

2019-08-13 Thread Rick J. Valles
This is what we use (from my friend, John C. Miller @ jmit.com ): //S1 EXEC PGM=ADRDSSU,PARM='TYPRUN=NORUN' //SYSPRINT DD SYSOUT=* //TAPE DD DUMMY //SYSINDD * DUMP DS(INC(**) BY(CATLG EQ NO)) OUTDD(TAPE) LOGINDYNAM(SYC500) r > On Aug 13, 2019, at 9:00 AM,

[SUSPECTED SPAM] Re: [SUSPECTED SPAM] Re: Instruction speeds

2019-08-13 Thread Gord Tomlin
On 2019-08-13 10:33, Mike Shaw wrote: JNE generates the same machine instruction as BNE, etc. Nope. Are you possibly fooling yourself by looking at code that uses IEABRC or IEABRCX? -- Regards, Gord Tomlin Action Software International (a division of Mazda Computer Corporation) Tel: (905)

Re: Instruction speeds

2019-08-13 Thread Christopher Y. Blaicher
Sorry, but 360 timings have no relevance to today's systems. Out-of-order processing, executing up to 6 instructions concurrently and a myriad of other factors make accurate timings impossible. Cache utilization is one of the biggest factors. Processing more data than the L1 and L2 caches can

Re: Instruction speeds

2019-08-13 Thread Brian Chapman
Thanks everyone for your input. I learned a lot from these responses. I actually meant to write ADD HALFWORD IMMEDIATE in my original email. I was surprised to hear about LA. I had assumed that direct register manipulation was the fastest. On the topic of cache, how do I know that my literal pool

Re: Instruction speeds

2019-08-13 Thread John McKown
On Tue, Aug 13, 2019 at 11:10 AM Brian Chapman wrote: > Thanks Charles and Steve. > > Now that I am becoming a more experience assembler programmer, I have > wondered if I should be greatly concerned about instruction timings or > pipeline order, or just simply focus on readability and

Re: WEEDING OUT DSNS WITH CATALOG ENTRIES ONLY

2019-08-13 Thread retired mainframer
I think you are looking for the DIAGNOSE command found in the AMS manual. It will compare the BCS and VVDS and identify mismatches in either direction. > -Original Message- > From: IBM Mainframe Discussion List On > Behalf Of esmie moo > Sent: Tuesday, August 13, 2019 7:37 AM > To:

Re: Instruction speeds

2019-08-13 Thread Tony Harminc
If you are interested in how these things work under the covers (regardless of whether it is possible or useful to minutely optimize your code these days), you might check out any of the several presentations done at SHARE and other places by Bob Rogers, now retired from IBM, under titles like

Re: Mainframes testing

2019-08-13 Thread Seymour J Metz
Item 3: Overprivileged Users Some shops do not allow multiple userids for a single user but do have users wearing multiple hats. That essentially force the user to do work with a userid that has more privileges than he need for the specific shop. -- Shmuel (Seymour J.) Metz

Re: ISPF Question - browsing variable length records

2019-08-13 Thread Seymour J Metz
> Why not? The host should transmit characters counted by the RDW, then NULs > to the end > of the field. Characters typed over those NULs would be returned to the host > on Read > Modified; the NULs ignored. Yes, ignored, not transmitted to the host. There will be no way to know which null

WEEDING OUT DSNS WITH CATALOG ENTRIES ONLY

2019-08-13 Thread esmie moo
Gentle Readers, Is there a way of weeding out dsns with cataloged entries only.  I tried DFDSS logical backup with NORUN option but it did not give me the desired results.  I coded the VOLSER of the disk to no avail.  I am doing this exercise in preparation of removing old dasd but experiences

Re: Instruction speeds

2019-08-13 Thread Seymour J Metz
The rules for assemblers are the same as the rules for any language processor: 1. Correctness trumps speed 2. Make it easier for somebody to figure out how it works and how to change it. Clever code is fine, but document it adequately. 3. When you change platforms or change

Re: NTP Server connectivity quandary

2019-08-13 Thread Dana Mitchell
On Tue, 13 Aug 2019 14:54:02 +, Mark Jacobs wrote: >Never saw this error before. > >Command failed, exit value is 2. >The command was [ping 10.2.8.62 -s 100 -c 5 -w 10] > >There is something wonky going on here. > Thats the message I receive if I try to ping a completely bogus address.

Re: Instruction speeds

2019-08-13 Thread Pew, Curtis G
On Aug 13, 2019, at 11:26 AM, Jesse 1 Robinson wrote: > > My advice is always to make it easy for next guy. Chances are, over time, the > 'next guy' will be the future you. Amen. The advice I give (I got it from Eric S. Raymond) is “Always write code as if the next person who will maintain

Re: [SUSPECTED SPAM] Re: Instruction speeds

2019-08-13 Thread Seymour J Metz
Not only no but hell no. JNE foo generates A74 with a mask of F, the same code as BRC 15,foo; BNE foo generates 47 with a mask of F, the same code as BC 15,foo. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Discussion

[SUSPECTED SPAM] Re: Instruction speeds

2019-08-13 Thread Mike Shaw
On 8/12/2019 9:33 PM, Christopher Y. Blaicher wrote: ..> JUMPs are faster than BRANCHes. . I don't know what you mean by that Chris. The various types of Jump instructions are just extended mnemonics for various types of Branch instructions. JNE generates the same machine

Re: Instruction speeds

2019-08-13 Thread Giliad Wilf
Hi Brian, I did not see this sort of publications for three or four decades. Maybe IBM zServer engineers still use some instruction timing charts during chip design/development. As far as I'm concerned, my emphasis while coding is on clarity and readability. Regards, On Tue, 13 Aug 2019

Re: [SUSPECTED SPAM] Re: Instruction speeds

2019-08-13 Thread Charles Mills
> JNE generates the same machine instruction as BNE, etc. Not really. The (old) branch instructions like BNE use a base register and a <4K displacement. The Jxx opcodes are synonyms for (new -- as in 20+ years) relative branch instructions which use a +/-64K relative displacement. The jumps

Re: Instruction speeds

2019-08-13 Thread Seymour J Metz
It's almost impossible to compare timings between processors except in the context of a well defined benchmark; run a different benchmark and you get a different answer. A classic example is comparing a 370/158 to a 4341; use packed decimal heavily and you get one answer; use floating point

Re: NTP Server connectivity quandary

2019-08-13 Thread Dana Mitchell
Ok, just for grins, lets try this: Go into 'Single Object Operations' for the CPC in question. Console Actions -> Network Diagnostic Information -> Ping tab. PING the address of the HMC you were trying to use as the sysplex time NTP Time Server. See if that SE can successfully ping that

Re: ISPF Question - browsing variable length records

2019-08-13 Thread Paul Gilmartin
On Tue, 13 Aug 2019 18:53:37 +, Seymour J Metz wrote: >> Does it matter? > >Not if you don't care whether the text is in the right column in your previous >request. > When I care, I set NULLS OFF, or use the spacebar. Usually it doesn't matter to me -- Rexx, C, shell script, ... >> I

Re: ISPF Question - browsing variable length records

2019-08-13 Thread Seymour J Metz
> Does it matter? Not if you don't care whether the text is in the right column in your previous request. > I accept that as a limitation of the 327x data stream design. I've exploited > it >at times to insert a character such as ';' at the end of a line when the cursor >is inconveniently

Re: ISPF Question - browsing variable length records

2019-08-13 Thread Seymour J Metz
> When I care, I set NULLS OFF, or use the spacebar. That's the right answer to the wrong question. You were asking about the ability to insert a blank in the middle of a string of nulls. > Which is why I didn't suggest IBM change it, nor change the 3270 > specification. You wrote "It should

Re: ISPF Question - browsing variable length records

2019-08-13 Thread Paul Gilmartin
On Tue, 13 Aug 2019 19:55:19 +, Seymour J Metz wrote: >> When I care, I set NULLS OFF, or use the spacebar. > >That's the right answer to the wrong question. You were asking about the >ability to insert a blank in the middle of a string of nulls. > No, I asked about adding a blank at the

Re: Mainframes testing

2019-08-13 Thread Jon Perryman
Is IBM trying to get out of z/OS? Abby Ross states "passwords and confidential information should not be on the mainframe because they are exposed to any type of user". This article is about selling IBM services and moving to Unix. So called experts yet she and her team obviously don't

Re: Instruction speeds

2019-08-13 Thread CM Poncelet
FWIW   On the Hitachi Skyline bipolar mainframe (from 1995), the instruction processor speeds were: - RR: 3ns. - SS: 6-10ns if L2 cached, else 60-80ns if data-fetched from central storage.   On IBM's CMOS G4 mainframes: - RR: 20ns approx. - SS: no idea, did not check.   IBM said it had 'improved'

Re: Instruction speeds

2019-08-13 Thread CM Poncelet
BTW Change "LHI   4,4096*512" and "LHI   5,4096*1024" to something like "LHI   4,4096*16-1"etc. or it will not fit in a halfword - just wrote it "off the top of my head" without checking. :-(   On 14/08/2019 03:24, CM Poncelet wrote: > FWIW >   > On the Hitachi Skyline bipolar mainframe (from

Re: Instruction speeds

2019-08-13 Thread Jim Mulder
This link has been posted here before, but in case anyone missed it, https://www.ibm.com/developerworks/community/files/form/anonymous/api/library/ff4563be-756e-49bf-9de9-6a04a08026f1/document/07c69512-ac74-4394-87b9-a61ea201347e/media/IBMzSystemsProcessorOptimizationPrimerv2.pdf Jim Mulder

Re: Mainframes testing

2019-08-13 Thread zMan
ITYM "surfeit" -- too MANY commenting without knowledge! But we knew what you meant. On Tue, Aug 13, 2019 at 8:54 AM Aled Hughes < 0050619ca8df-dmarc-requ...@listserv.ua.edu> wrote: > You and me both Lennie > > "Abby is a seasoned marketing and public relations professional." > Reminds

Re: Instruction speeds

2019-08-13 Thread Giliad Wilf
On Mon, 12 Aug 2019 20:48:18 -0400, Brian Chapman wrote: >Hi everyone, > >I did some searching, but I didn't find anything that really discussed this >on the topic that I'm interested. Is there anything published that compares >the cycle times of the most used instructions? > >For example;

Re: NTP Server connectivity quandary

2019-08-13 Thread Mark Jacobs
Never saw this error before. Command failed, exit value is 2. The command was [ping 10.2.8.62 -s 100 -c 5 -w 10] There is something wonky going on here. Thanks for the idea. Mark Jacobs Sent from ProtonMail, Swiss-based encrypted email. GPG Public Key -

Re: Instruction speeds

2019-08-13 Thread Brian Chapman
Thanks Charles and Steve. Now that I am becoming a more experience assembler programmer, I have wondered if I should be greatly concerned about instruction timings or pipeline order, or just simply focus on readability and maintenance. Especially since assembler programming is becoming a dying

Re: Mainframes testing

2019-08-13 Thread Robert Longabaugh
"The mainframe was and is critical to commercial databases, transaction..." "The mainframe is critical to commercial databases, transaction..." <=== FIXED IT Bob Longabaugh Broadcom Storage Management On Tue, Aug 13, 2019 at 10:26 AM Seymour J Metz wrote: > Item 3: Overprivileged Users > >

Re: Mainframes testing

2019-08-13 Thread Lennie Dymoke-Bradshaw
Filip, The IBM paper reads as if it has been written by someone with relatively little System z knowledge. " There can also be security flaws created during the set-up of permissions for libraries. Libraries are modules for coding. They call into the code and should only be accessed by people

Re: Mainframes testing

2019-08-13 Thread Lennie Dymoke-Bradshaw
It would nice to think that IBM could comment on their own platform with a little more authority and accuracy. After all System z income has sustained IBM over the last 25 years. Without the enormous annuity income from their System z customers IBM would have gone down the tubes years ago.

Re: Mainframes testing

2019-08-13 Thread Charles Mills
I disagree somewhat with the other two commenters. The papers are NOT an advanced how-to for RACF administrators! (For that, see the DISA STIGs!) But they are a decent intro for a manager who is ignorant of -- and frankly, need not be concerned with -- configuration details. They weren't

Re: Instruction speeds

2019-08-13 Thread Charles Mills
I second everything Chris Blaicher says. You just cannot say how long an instruction takes. Let me give you an example. (The example is based on theoretical concepts and has not been tested or benchmarked.) Let's say you had some tight loop that was executed many thousands or millions of

Re: Source of initial HMC backup

2019-08-13 Thread Christian Svensson
Hi, I managed to get a backup going by copying /console/data/iqyvpdc.xml from my SE to my HMC and then running the backup. It seems to work just fine, but if anyone can confirm / deny the sanity of doing that it would be greatly appreciated :-). Thanks, On Mon, Aug 12, 2019 at 6:12 PM Christian

Re: Mainframes testing

2019-08-13 Thread Aled Hughes
You and me both Lennie "Abby is a seasoned marketing and public relations professional." Reminds me that a journalist called Ruth Sunderland was on the radio the other day stating that the airline British Airways (after a failure) "is riddled with old systems that have been in place for

Re: NTP Server connectivity quandary

2019-08-13 Thread Dana Mitchell
On Mon, 12 Aug 2019 21:08:58 +, Mark Jacobs wrote: > >Went back to the Sysplex time task, used that IP address as the ETS source, >same communications failure. > >I'm at a loss. > Me too, thats how ours are set up. Do you have the STP feature? (is it optional on z13?). Defined CPCs ->

Re: NTP Server connectivity quandary

2019-08-13 Thread Mark Jacobs
Yes. We have STP. It's currently unconfigured. I'm waiting until I get NTP services setup before I setup the CTN. Timing network type: Unconfigured Coordinated timing network (CTN) ID: Timing state: Unsynchronized Usable clock source:No Timing mode:Local Maximum timing stratum level: