On Mon, Jul 18, 2011 at 11:19:17AM -0700, Eric Anholt wrote:
> On Sun, 17 Jul 2011 16:25:42 -0700, Ben Widawsky wrote:
> > Upload the system routine as part of the invariant state if debugging.
> >
> > Remove SIP setting if not debugging to make it more friendly for others
> > that may be debuggi
Move intel-agp module dependence check into device probe function
instead of always checking that when loading i915 module, which seems
too chatty on non-intel graphics device.
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/i915/i915_drv.c | 10 +-
1 files changed, 5 insertions(+), 5 d
On 07/18/2011 05:08 PM, Chad Versace wrote:
> Until now, the stencil buffer was allocated as a Y tiled buffer, because
> in several locations the PRM states that it is. However, it is actually
> W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section
> 4.5.2.1 W-Major Format:
> W-Ma
Until now, the stencil buffer was allocated as a Y tiled buffer, because
in several locations the PRM states that it is. However, it is actually
W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section
4.5.2.1 W-Major Format:
W-Major Tile Format is used for separate stencil.
The GTT
Until now, the stencil buffer was allocated as a Y tiled buffer, because
in several locations the PRM states that it is. However, it is actually
W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section
4.5.2.1 W-Major Format:
W-Major Tile Format is used for separate stencil.
The GTT
Patch 1 v2:
- Change buffer height from ALIGN(height / 2, 64) to
ALIGN((height + 1) / 2, 64).
Patch 2 v2:
- Change buffer height from ALIGN(height / 2, 64) to
ALIGN((height + 1) / 2, 64).
- Change return type of intel_offset_S8 changed to intptr_t.
- Improve performance of Y_
On 07/18/2011 08:57 AM, Eric Anholt wrote:
> On Mon, 18 Jul 2011 00:55:03 -0700, Chad Versace wrote:
>> diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
>> b/src/mesa/drivers/dri/intel/intel_fbo.c
>> index 1669af2..507cc33 100644
>> --- a/src/mesa/drivers/dri/intel/intel_fbo.c
>> +++ b/src/mes
On Tue, 19 Jul 2011 00:48:23 +0200, Paul Menzel
wrote:
Non-text part: multipart/mixed
Non-text part: multipart/signed
> Am Montag, den 18.07.2011, 13:31 -0700 schrieb Keith Packard:
> I have not been able to test this patch but if it fixes the issue it
> should definitely be sent to stable as we
Am Montag, den 18.07.2011, 13:31 -0700 schrieb Keith Packard:
> On Mon, 18 Jul 2011 17:57:52 +0100, Chris Wilson
> wrote:
>
> > Keith, apologies your missive arrived as I sent the previous patch. This
> > uses the inferface you proposed..
>
> Thanks! I've reduced the diff a bit more to make it
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On 07/18/2011 02:24 PM, Chad Versace wrote:
> On 07/18/2011 02:02 PM, Ian Romanick wrote:
>> On 07/18/2011 01:54 PM, Chad Versace wrote:
>>> On 07/18/2011 11:49 AM, Ian Romanick wrote:
On 07/18/2011 12:55 AM, Chad Versace wrote:
> Until now, t
On 07/18/2011 02:02 PM, Ian Romanick wrote:
> On 07/18/2011 01:54 PM, Chad Versace wrote:
>> On 07/18/2011 11:49 AM, Ian Romanick wrote:
>>> On 07/18/2011 12:55 AM, Chad Versace wrote:
Until now, the stencil buffer was allocated as a Y tiled buffer, because
in several locations the PRM st
On 07/18/2011 08:57 AM, Eric Anholt wrote:
> On Mon, 18 Jul 2011 00:55:03 -0700, Chad Versace wrote:
>> diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
>> b/src/mesa/drivers/dri/intel/intel_fbo.c
>> index 1669af2..507cc33 100644
>> --- a/src/mesa/drivers/dri/intel/intel_fbo.c
>> +++ b/src/mes
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On 07/18/2011 01:54 PM, Chad Versace wrote:
> On 07/18/2011 11:49 AM, Ian Romanick wrote:
>> On 07/18/2011 12:55 AM, Chad Versace wrote:
>>> Until now, the stencil buffer was allocated as a Y tiled buffer, because
>>> in several locations the PRM state
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On 07/18/2011 12:28 PM, Chad Versace wrote:
> On 07/18/2011 11:45 AM, Ian Romanick wrote:
>> On 07/18/2011 12:55 AM, Chad Versace wrote:
>>> Until now, the stencil buffer was allocated as a Y tiled buffer, because
>>> in several locations the PRM state
On 07/18/2011 11:49 AM, Ian Romanick wrote:
> On 07/18/2011 12:55 AM, Chad Versace wrote:
>> Until now, the stencil buffer was allocated as a Y tiled buffer, because
>> in several locations the PRM states that it is. However, it is actually
>> W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Par
On Mon, 18 Jul 2011 17:57:52 +0100, Chris Wilson
wrote:
> Keith, apologies your missive arrived as I sent the previous patch. This
> uses the inferface you proposed..
Thanks! I've reduced the diff a bit more to make it easier to review and
have pushed this patch onto drm-intel-fixes. I'd like t
On 07/18/2011 11:45 AM, Ian Romanick wrote:
> On 07/18/2011 12:55 AM, Chad Versace wrote:
>> Until now, the stencil buffer was allocated as a Y tiled buffer, because
>> in several locations the PRM states that it is. However, it is actually
>> W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Par
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On 07/18/2011 12:55 AM, Chad Versace wrote:
> Until now, the stencil buffer was allocated as a Y tiled buffer, because
> in several locations the PRM states that it is. However, it is actually
> W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part
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On 07/18/2011 12:55 AM, Chad Versace wrote:
> Until now, the stencil buffer was allocated as a Y tiled buffer, because
> in several locations the PRM states that it is. However, it is actually
> W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part
On Sun, 17 Jul 2011 16:25:42 -0700, Ben Widawsky wrote:
> Upload the system routine as part of the invariant state if debugging.
>
> Remove SIP setting if not debugging to make it more friendly for others
> that may be debugging shaders or media kernels.
>
> v2: removed comment per Chris
This p
On Wed, 13 Jul 2011 13:51:44 -0700, Ben Widawsky wrote:
> The debugger shared memory needs to be a fixed size. Since this is
> scratch memory that is already used by register spilling, add
> appropriate hooks to do the right thing when debugging.
>
> v2: Include the bytes for a known good system
On Mon, 18 Jul 2011 00:55:03 -0700, Chad Versace wrote:
> diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
> b/src/mesa/drivers/dri/intel/intel_fbo.c
> index 1669af2..507cc33 100644
> --- a/src/mesa/drivers/dri/intel/intel_fbo.c
> +++ b/src/mesa/drivers/dri/intel/intel_fbo.c
> @@ -173,6 +173,9
Align unfenced buffers on older hardware to the power-of-two object size.
The docs suggest that it should be possible to align only to a power-of-two
tile height, but using the already computed fence size is easier and
always correct. We also have to make sure that we unbind misaligned buffers
upon
Align unfenced buffers on older hardware to the power-of-two object size.
The docs suggest that it should be possible to align only to a power-of-two
tile height, but using the already computed fence size is easier and
always correct. We also have to make sure that we unbind misaligned buffers
upon
On Mon, 18 Jul 2011 09:17:16 -0700, Keith Packard wrote:
Non-text part: multipart/signed
> On Sat, 9 Jul 2011 09:31:25 +0100, Chris Wilson
> wrote:
>
> > uint32_t
> > -i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
> > +i915_gem_get_unfenced_gtt_alignment(struct drm_i915
On Mon, 18 Jul 2011 09:17:16 -0700, Keith Packard wrote:
Non-text part: multipart/signed
> On Sat, 9 Jul 2011 09:31:25 +0100, Chris Wilson
> wrote:
>
> > uint32_t
> > -i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
> > +i915_gem_get_unfenced_gtt_alignment(struct drm_i915
On Sat, 9 Jul 2011 09:31:25 +0100, Chris Wilson
wrote:
> uint32_t
> -i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
> +i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj,
> + int tiling_mode)
...
> + return i915_gem_get
It sucks a bit to see the relaxed fencing idea go down the toilet for pre-g33,
but bleh, hw sometimes just hates us.
Cc: sta...@kernel.org
Reviewed-by: Daniel Vetter
--
Daniel Vetter
daniel.vet...@ffwll.ch - +41 (0) 79 364 57 48 - http://blog.ffwll.ch
Hello,
My problem is TV doesn't receive audio through jack 3.5, because my
video card send null packets by hdmi output.
Here this part of intel_audio_dump:
SDVOC HDMI encoding1
SDVOC SDVO encoding0
SDVOC null packets1
SDVOC audio enabled1
I solv
Am Montag, den 18.07.2011, 00:55 -0700 schrieb Chad Versace:
[…]
> diff --git a/src/mesa/drivers/dri/intel/intel_span.c
> b/src/mesa/drivers/dri/intel/intel_span.c
> index 153803f..d306432 100644
> --- a/src/mesa/drivers/dri/intel/intel_span.c
> +++ b/src/mesa/drivers/dri/intel/intel_span.c
> @@
Am Montag, den 18.07.2011, 00:55 -0700 schrieb Chad Versace:
> Until now, the stencil buffer was allocated as a Y tiled buffer, because
> in several locations the PRM states that it is. However, it is actually
> W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section
> 4.5.2.1 W-Major F
Until now, the stencil buffer was allocated as a Y tiled buffer, because
in several locations the PRM states that it is. However, it is actually
W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section
4.5.2.1 W-Major Format:
W-Major Tile Format is used for separate stencil.
The GTT
Until now, the stencil buffer was allocated as a Y tiled buffer, because
in several locations the PRM states that it is. However, it is actually
W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section
4.5.2.1 W-Major Format:
W-Major Tile Format is used for separate stencil.
The GTT
Chad Versace (2):
xf86-video-intel
dri: Do not tile stencil buffer
src/intel_dri.c | 16
mesa
intel: Fix stencil buffer to be W tiled
src/mesa/drivers/dri/intel/intel_clear.c |6 ++
src/mesa/drivers/dri/intel/intel_context.c |9 ++-
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