On Thu, Apr 12, 2012 at 01:59:07AM +, James wrote:
> Hello! I know this is an old thread, but i am having this problem on my
> macbook
> air. Ideas for a quick fix?
Upgrade to kernel 3.2 or newer, that has the patch.
-Daniel
--
Daniel Vetter
Mail: dan...@ffwll.ch
Mobile: +41 (0)79 365 57 48
Hello! I know this is an old thread, but i am having this problem on my macbook
air. Ideas for a quick fix?
Thanks,
James
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There are many bugs open on fd.o regarding missing modes that are supported on
Windows and other closed source drivers.
>From EDID spec we can (might?) infer modes using GTF and CVT when monitor
>allows it trough range limited flag... obviously limiting by the range.
>From our code:
* EDID spec
There are many bugs open on fd.o regarding missing modes that are supported on
Windows and other closed source drivers.
>From EDID spec we can (might?) infer modes using GTF and CVT when monitor
>allows it trough range limited flag... obviously limiting by the range.
>From our code:
* EDID spec
There are many bugs open on fd.o regarding missing modes that are supported on
Windows and other closed source drivers.
>From EDID spec we can (might?) infer modes using GTF and CVT when monitor
>allows it trough range limited flag... obviously limiting by the range.
>From our code:
* EDID spec
On Wed, 11 Apr 2012 22:12:45 +0200, Daniel Vetter
wrote:
> Hi all,
>
> This patch series is inspired by Ben's ring->get|put_irq cleanup for gen6+ and
> my perpetual hatred for intel_ringbuffer.c.
>
> It's a lot of churn, but the end result is imho worth it - I almost started to
> like what the
On Thu, 12 Apr 2012 01:27:57 +0200, Daniel Vetter
wrote:
> This fixes a regression introduce in
s/introduce/introduced/
> commit 7dd4906586274f3945f2aeaaa5a33b451c3b4bba
> Author: Chris Wilson
> Date: Wed Mar 21 10:48:18 2012 +
>
> drm/i915: Mark untiled BLT commands as fenced on ge
This fixes a regression uncovered by
commit 7dd4906586274f3945f2aeaaa5a33b451c3b4bba
Author: Chris Wilson
Date: Wed Mar 21 10:48:18 2012 +
drm/i915: Mark untiled BLT commands as fenced on gen2/3
which fixed fencing tracking for untiled blt commands.
A side effect of that patch was th
This fixes a regression introduce in
commit 7dd4906586274f3945f2aeaaa5a33b451c3b4bba
Author: Chris Wilson
Date: Wed Mar 21 10:48:18 2012 +
drm/i915: Mark untiled BLT commands as fenced on gen2/3
which fixed fencing tracking for untiled blt commands.
A side effect of that patch was th
Greg KH wrote:
> Argh, it just missed the cutoff for the next 3.2-stable release, sorry,
> this will have to wait for the next one, the build machines are already
> underway at the moment with the tests...
No problem. As long as it enters the tree soonish, I'm happy. :)
_
Hi Greg,
Keith Packard wrote:
> On Thu, 12 Jan 2012 14:51:17 -0800, Jesse Barnes
> wrote:
>> The transcoder port may changed from mode set to mode set, so make sure
>> to mask out the selection bits before setting the right ones or we'll
>> get black screens when going from transcoder B to A.
>
On Wed, Apr 11, 2012 at 11:10:05PM +0100, Chris Wilson wrote:
> On Wed, 11 Apr 2012 09:14:43 +0100, Chris Wilson
> wrote:
> > I'm down to just bikeshedding over useless lines of code which do not
> > even add visual clarity...
> >
> > Reviewed-by: Chris Wilson
>
> Oops, need to learn to spot 6
May one day prove invaluable in debugging spurious fencing issues.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b505b70
On Wed, 11 Apr 2012 09:14:43 +0100, Chris Wilson
wrote:
> I'm down to just bikeshedding over useless lines of code which do not
> even add visual clarity...
>
> Reviewed-by: Chris Wilson
Oops, need to learn to spot 64-bit divides which become an issue on
32-bit builds.
diff --git a/drivers/gp
PCH PLLs aren't required for outputs on the CPU, so we shouldn't just
treat them as part of the pipe.
So split the code out and manage PCH PLLs separately, allocating them
when needed or trying to re-use existing PCH PLL setups when the timings
match.
v2: add num_pch_pll field to dev_priv (Daniel
On Wed, 11 Apr 2012 22:12:45 +0200, Daniel Vetter
wrote:
> Hi all,
>
> This patch series is inspired by Ben's ring->get|put_irq cleanup for gen6+ and
> my perpetual hatred for intel_ringbuffer.c.
>
> It's a lot of churn, but the end result is imho worth it - I almost started to
> like what the
On Wed, 11 Apr 2012 09:18:15 +0100
Chris Wilson wrote:
> On Tue, 10 Apr 2012 16:59:11 -0700, Ben Widawsky wrote:
> > On Tue, 10 Apr 2012 17:00:41 +0100
> > Chris Wilson wrote:
> >
> > > On the first instance we just wish to kick the waiters and see if that
> > > terminates the wait conditions.
Now that these are properly refactored this additional indirection
doesn't really buy us anything but confusion. Hence inline them.
This duplicates the ironlake gt enable/disable code snippet, but we've
already separate ilk from gen6+ gt irq in i915_irq.c, so I think this
makes more sense.
Signed
We already disallow initialition of gem in this case in the
corresponding ioctl, so don't bother setting up the gem support ring
functions in the legacy dri render ring init.
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 24 ++--
1 files changed
They're indentical, so just kill one. Also give the other a prefix to
distinguish it from the gen6+ functions - this add_request function is
not really generic code.
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 29 -
1 files changed, 4
Now that we can, we should split them up in a way that makes some
sense and banishes the IS_ checks into init code.
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 69 ++-
1 files changed, 40 insertions(+), 29 deletions(-)
diff --git a/dr
HW engineers have fixed this issue for ivb. Again, a nice cleanup
possible thanks to the more flexible ring initialization.
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/
Now that we have sensibly split up, we can nicely get rid of that ugly
is_gen5 check.
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 66 --
1 files changed, 44 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbu
Inspired by Ben Widawsky's patch for gen6+. Now after restructuring
how we set up the ring vtables and parameters, we can do this right.
This kills the bsd specific get/put_irq functions, they're now the
same.
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 77 +
The waiter is always the ring itself (otherwise we'd have a decent
snafu in a callsite), so we can unify this easily.
Also give it the usual gen6_ prefix, in case anyone is foolish enough to
implement hw semaphores for gen5.
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer
It's not supported, and with the patch to refuse loading on gen6+
without kms enabled, there's also no way we can hit this.
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++
1 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/
Just for consistency.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 40 ++
1 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 32ff8c7.
The same treatment for the bds ring. Again, this will be split up
further by the irq rework.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 72 +-
1 files changed, 31 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel
Our hw is simply not well-designed enough that it neatly fits into
boxes. Everywhere else we set up vtables and similar things
dynamically using switch statements - it's simply much more flexible.
This is prep work to rework the pre-gen6 ring irq stuff - it'll add a
few more differences. With the
Eventually we want to scale the ring size depending upon available
gtt space. For now just consolidate this instead of replicating it
over all ringbuffer templates.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ringbuffer.c |5 +
1 files changed, 1 insertions(+), 4 deletion
We only ever enable/disable one interrupt (namely user_interrupts and
pipe_notify), so we don't need to track the interrupt masking state.
Also rename irq_enable to irq_enable_mask, now that it won't collide -
beforehand both a irq_mask and irq_enable_mask would have looked a bit
strange.
Signed-
Hi all,
This patch series is inspired by Ben's ring->get|put_irq cleanup for gen6+ and
my perpetual hatred for intel_ringbuffer.c.
It's a lot of churn, but the end result is imho worth it - I almost started to
like what the ringbuffer abstraction looks like now. There are some follow-up
cleanups
Our workaround list kindly lists that this new default value needs to
be updated in Bspec. Naturally, this did not happen.
Acked-by: Ben Widawsky
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c |4
2 files changed, 5
According to Bsepc, this should be set by default, but isn't. See vo1c.4
"Render Engine Command Streamer", Section 1.1.14.3 "3D_CHICKEN3"
Bspec also says that we always need to set all mask bits.
v2: Add comment about the mask bits wtf.
Reviewed-by: Ben Widawsky
Signed-off-by: Daniel Vetter
--
For some reason snb has 2 fields to set ppgtt cacheability. This one
here does not exist on gen7.
This might explain why ppgtt wasn't a win on snb like on ivb - not
enough pte caching.
v2: Fixup rebase fail.
Reviewed-by: Ben Widawsky
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_
Bspec says that we need to set this: vol1c.3 "Blitter Command
Streamer", Section 1.1.2.1 "GAB_CTL_REG - GAB Unit Control Register".
We don't really rely on pagefaults, but who knows what this all
affects.
Reviewed-by: Ben Widawsky
Signed-Off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem.
Contrary to the other clock gating w/a in GEN6_UCGCTL1, this one is
actually documented in Bspec, vol1g "GT Interface Registers [SNB]",
Section 1.5.1 "UCGCTL1 - Unit Level Clock Gating Control 1".
Supposedly this can prevent hangs on the media ring.
Reviewed-by: Ben Widawsky
Signed-Off-by: Danie
On Wed, Apr 11, 2012 at 09:39:02AM -0700, Jesse Barnes wrote:
> People have been getting confused and thinking this is a runtime control.
>
> Cc: sta...@vger.kernel.org
> Signed-off-by: Jesse Barnes
Picked up for -fixes, thanks for the patch.
-Daniel
--
Daniel Vetter
Mail: dan...@ffwll.ch
Mobile
On Wed, Apr 11, 2012 at 07:41:04PM +0100, Chris Wilson wrote:
> On Wed, 11 Apr 2012 11:18:19 -0700, Ben Widawsky wrote:
> > When I extracted the synchronization code for implementing semaphorified
> > pageflips (74f5f6e0), I neglected the non pipelined case which also
> > calls this code. The mode
On Wed, 11 Apr 2012 11:18:21 -0700, Ben Widawsky wrote:
> Waiting for seqno-1 in our object synchronization code is an
> implementation detail given how we've decided to do the waits within the
> rest of our code.
>
> Requested-by: Daniel Vetter
> Signed-off-by: Ben Widawsky
Thanks for the com
On Wed, 11 Apr 2012 11:18:20 -0700, Ben Widawsky wrote:
> This fixes a long standing issue where emitting the semaphore updates
> may have failed, but we've already updated our internal data structure.
>
> Reported-by: Daniel Vetter
> Signed-off-by: Ben Widawsky
I would have written it as ret
On Wed, 11 Apr 2012 11:18:19 -0700, Ben Widawsky wrote:
> When I extracted the synchronization code for implementing semaphorified
> pageflips (74f5f6e0), I neglected the non pipelined case which also
> calls this code. The modesetting code wants to make sure the object has
> finished rendering to
PCH PLLs aren't required for outputs on the CPU, so we shouldn't just
treat them as part of the pipe.
So split the code out and manage PCH PLLs separately, allocating them
when needed or trying to re-use existing PCH PLL setups when the timings
match.
Fixes https://bugs.freedesktop.org/show_bug.c
On Wed, Apr 11, 2012 at 09:23:34AM -0700, Jesse Barnes wrote:
> When the PCH split occurred, we dropped support for separate hsync and
> vsync disable in the VGA DAC. So add a PCH specific DPMS function that
> just uses the port enable bit for controlling DPMS states.
>
> Before this fix, when an
Waiting for seqno-1 in our object synchronization code is an
implementation detail given how we've decided to do the waits within the
rest of our code.
Requested-by: Daniel Vetter
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem.c |2 +-
drivers/gpu/drm/i915/intel_ringb
This fixes a long standing issue where emitting the semaphore updates
may have failed, but we've already updated our internal data structure.
Reported-by: Daniel Vetter
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
When I extracted the synchronization code for implementing semaphorified
pageflips (74f5f6e0), I neglected the non pipelined case which also
calls this code. The modesetting code wants to make sure the object has
finished rendering to the frame before configuring the scanout (ie.
non-pipelined case
On Wed, 11 Apr 2012 09:39:02 -0700, Jesse Barnes
wrote:
> People have been getting confused and thinking this is a runtime control.
>
> Cc: sta...@vger.kernel.org
> Signed-off-by: Jesse Barnes
But with Danvet's new reset code, you could
echo 1 > /sys/modules/i915/parameters/i915_enable_rc6
ech
On Wed, 11 Apr 2012 09:23:36 -0700
Jesse Barnes wrote:
> This is a hack to make sure CPU eDP mode sets avoid allocating a PCH PLL.
Ignore this one, it's too ugly to live. I'll put something better
together now...
--
Jesse Barnes, Intel Open Source Technology Center
signature.asc
Description
People have been getting confused and thinking this is a runtime control.
Cc: sta...@vger.kernel.org
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i9
This is a hack to make sure CPU eDP mode sets avoid allocating a PCH PLL.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c |2 ++
drivers/gpu/drm/i915/intel_dp.c |4
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_di
We'll probably need new init functions and will need to test it.
v2: fix impossible GEN6 && GEN7 condition, move to Daniel's new init function
Signed-off-by: Jesse Barnes
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c |4 ++--
1 files changed, 2 insertions(+), 2 dele
When the PCH split occurred, we dropped support for separate hsync and
vsync disable in the VGA DAC. So add a PCH specific DPMS function that
just uses the port enable bit for controlling DPMS states.
Before this fix, when anything other than a full DPMS off occurred,
the VGA port would be left e
On IVB, there are two sets of panel backlight regs: one in the CPU and
one in the PCH. The CPU ones aren't generally used, so on IVB make sure
we allow the PCH regs to actually control the backlight.
v2: remove unused pwm variable (Daniel)
move to init_hw function so we override on resume too
On Tue, Apr 10, 2012 at 10:26:56PM +0100, Chris Wilson wrote:
> On Tue, 10 Apr 2012 11:58:04 -0700, Jesse Barnes
> wrote:
> > If these regs don't have valid values, the panel won't come up, and may
> > even cause a system hang. So do a basic sanity check when an eDP panel
> > is detected.
> >
>
On Wed, 11 Apr 2012 16:52:33 +0100
Chris Wilson wrote:
> On Wed, 11 Apr 2012 08:46:40 -0700, Ben Widawsky wrote:
> > On Wed, 11 Apr 2012 14:06:42 +0200
> > Daniel Vetter wrote:
> >
> > > On Wed, Apr 11, 2012 at 12:53:15PM +0100, Chris Wilson wrote:
> > > > On Thu, 5 Apr 2012 14:47:36 -0700, B
On Wed, 11 Apr 2012 11:53:55 +0200
Daniel Vetter wrote:
> On Tue, Apr 10, 2012 at 10:22:09PM +0100, Chris Wilson wrote:
> > On Tue, 10 Apr 2012 11:58:03 -0700, Jesse Barnes
> > wrote:
> > > Both PCH and CPU eDP are DP, so set the is_dp flag to true. Add
> > > is_cpu_edp and is_pch_edp bools to
On Wed, 11 Apr 2012 08:46:40 -0700, Ben Widawsky wrote:
> On Wed, 11 Apr 2012 14:06:42 +0200
> Daniel Vetter wrote:
>
> > On Wed, Apr 11, 2012 at 12:53:15PM +0100, Chris Wilson wrote:
> > > On Thu, 5 Apr 2012 14:47:36 -0700, Ben Widawsky
> > > wrote:
> > > > In theory this will have performan
On Wed, 11 Apr 2012 14:06:42 +0200
Daniel Vetter wrote:
> On Wed, Apr 11, 2012 at 12:53:15PM +0100, Chris Wilson wrote:
> > On Thu, 5 Apr 2012 14:47:36 -0700, Ben Widawsky wrote:
> > > In theory this will have performance and power improvements. Performance
> > > because we don't need to stall
On Wed, Apr 11, 2012 at 12:53:15PM +0100, Chris Wilson wrote:
> On Thu, 5 Apr 2012 14:47:36 -0700, Ben Widawsky wrote:
> > In theory this will have performance and power improvements. Performance
> > because we don't need to stall when the scanout BO is busy, and power
> > because we don't have t
On Thu, 5 Apr 2012 14:47:36 -0700, Ben Widawsky wrote:
> In theory this will have performance and power improvements. Performance
> because we don't need to stall when the scanout BO is busy, and power
> because we don't have to stall when the BO is busy (and the ring can
> even go to sleep if th
On Tue, Apr 10, 2012 at 03:24:13PM -0700, Ben Widawsky wrote:
> On Sat, Mar 31, 2012 at 11:21:57AM +0200, Daniel Vetter wrote:
> > According to an internal workaround master list, we need to set bit 5
> > of register 9400 to avoid issues with color blits.
> >
> > Signed-Off-by: Daniel Vetter
>
>
On Mon, Apr 09, 2012 at 01:59:46PM +0100, Chris Wilson wrote:
> The 845g shares the errata with i830 whereby executing a command
> within 2 cachelines of the end of the ringbuffer may cause a GPU hang.
>
> Signed-off-by: Chris Wilson
> Cc: sta...@kernel.org
Picked up for -fixes, thanks for the pa
On Mon, Apr 09, 2012 at 08:31:20PM +0100, Chris Wilson wrote:
> On Mon, 9 Apr 2012 21:10:38 +0200, Daniel Vetter
> wrote:
> > This reverts commit c3dfefa0a6d235bd465309e12f4c56ea16e7.
> >
> > gmbus in 3.4 has simply too many known issues:
> > - gmbus is too noisy, we need to rework the logg
On Tue, Apr 10, 2012 at 10:35:19PM +0100, Chris Wilson wrote:
> On Tue, 10 Apr 2012 11:52:50 +0100, Chris Wilson
> wrote:
> > Similar to allowing a buffer to be simultaneously read by the GPU and
> > through the GTT, we wish to allow readback of the pages through the CPU
> > domain whilst they ar
On Tue, Apr 10, 2012 at 03:10:23PM +0100, Chris Wilson wrote:
> On Tue, 10 Apr 2012 15:50:11 +0200, Daniel Vetter
> wrote:
> > After a gpu reset we need to re-init some of the hw state we only
> > initialize when modeset is enabled, like rc6, hw contexts or render/GT
> > core clock gating and wor
On Tue, Apr 10, 2012 at 04:33:38PM +0100, Chris Wilson wrote:
> On Tue, 10 Apr 2012 17:29:17 +0200, daniel.vet...@ffwll.ch wrote:
> > From: Daniel Vetter
> >
> > We don't need the pt_addr for the !dmar case, so drop the else and
> > move the if (dmar) condition out of the loop.
> >
> > v2: Fixup
On Tue, Apr 10, 2012 at 10:22:09PM +0100, Chris Wilson wrote:
> On Tue, 10 Apr 2012 11:58:03 -0700, Jesse Barnes
> wrote:
> > Both PCH and CPU eDP are DP, so set the is_dp flag to true. Add
> > is_cpu_edp and is_pch_edp bools to make checking for each less verbose
> > (rather than has_edp_encode
On Wed, Apr 11, 2012 at 09:14:43AM +0100, Chris Wilson wrote:
> On Tue, 10 Apr 2012 21:17:01 -0700, Ben Widawsky wrote:
> > Merge rc6 information into the power group for our device. Until now the
> > i915 driver has not had any sysfs entries (aside from the connector
> > stuff enabled by drm core
Am Mittwoch, den 11.04.2012, 08:24 + schrieb Sun, Yi:
[…]
> Thank all your comments.
Thank you for your prompt reply and your work on the Intel-gfx driver.
Thanks,
Paul
signature.asc
Description: This is a digitally signed message part
___
Int
> > We finished a new round of kernel testing. The version of kernel is:
> > Kernel: (drm-intel-testing)9d0b5b5468650e0ac72a7786cf6625963f926d4d
> > Merge: ec34a01 b4db1e3
> > Author: Daniel Vetter
> > Date: Mon Apr 9 18:12:03 2012 +0200
> >
> > We covered the platform IvyBridge, SandyBridge, Ir
On Tue, 10 Apr 2012 16:59:11 -0700, Ben Widawsky wrote:
> On Tue, 10 Apr 2012 17:00:41 +0100
> Chris Wilson wrote:
>
> > On the first instance we just wish to kick the waiters and see if that
> > terminates the wait conditions. If it does not, then we do not want to
> > keep retrying without eve
On Tue, 10 Apr 2012 21:17:01 -0700, Ben Widawsky wrote:
> Merge rc6 information into the power group for our device. Until now the
> i915 driver has not had any sysfs entries (aside from the connector
> stuff enabled by drm core). Since it seems like we're likely to have
> more in the future I cre
Dear Yi¹,
Am Mittwoch, den 11.04.2012, 03:20 + schrieb Sun, Yi:
> We finished a new round of kernel testing. The version of kernel is:
> Kernel: (drm-intel-testing)9d0b5b5468650e0ac72a7786cf6625963f926d4d
> Merge: ec34a01 b4db1e3
> Author: Daniel Vetter
> Date: Mon Apr 9 18:12:03 2012 +02
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